From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Schwierzeck Date: Tue, 11 Sep 2018 17:53:53 +0200 Subject: [U-Boot] [PATCH v1 1/4] MIPS: cache: reimplement dcache_[status, enable, disable] In-Reply-To: <8152840d-a71b-beb5-0415-fb17a378b614@denx.de> References: <20180907170206.22586-1-daniel.schwierzeck@gmail.com> <20180907170206.22586-2-daniel.schwierzeck@gmail.com> <8152840d-a71b-beb5-0415-fb17a378b614@denx.de> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Am Di., 11. Sep. 2018 um 16:30 Uhr schrieb Stefan Roese : > > On 11.09.2018 16:12, Daniel Schwierzeck wrote: > > Am Mo., 10. Sep. 2018 um 07:34 Uhr schrieb Stefan Roese : > >> > >> Hi Daniel, > >> > >> On 07.09.2018 19:02, Daniel Schwierzeck wrote: > >>> Those functions are not needed during cache init and can be > >>> implemented in C. Only support the safe disabling of caches when > >>> this is required for booting an OS. Reenabling caches is much > >>> harder to implement if an optional coherency manager must be > >>> supported. As there is no real use-case anyway, dcache_enable > >>> is implemented with an error message. > >>> > >>> Signed-off-by: Daniel Schwierzeck > >> > >> Many thanks for working on this. I'll be doing some more test > >> later this week using this series. One comment though directly: > >> > >> A few weeks ago I wanted to enable the "cache" cmd (CMD_CACHE) > >> on my MT7688 MIPS platform. Unfortunately some I-Cache functions > >> are missing for this: > >> > >> building ... > >> cmd/built-in.o: In function `do_icache': > >> cmd/cache.c:(.text.do_icache+0x48): undefined reference to `icache_disable' > >> cmd/cache.c:(.text.do_icache+0x68): undefined reference to `icache_enable' > >> cmd/cache.c:(.text.do_icache+0x88): undefined reference to `icache_status' > >> Makefile:1350: recipe for target 'u-boot' failed > >> > >> Would it be possible to add those functions as well to this > >> series (or some follow-up patch)? Using the cache cmd can be > >> quite helpful while testing / debugging. > >> > > > > The problem is that you can't independently disable I-Cache and > > D-Cache on MIPS. > > Why is this the case? Can't the I-Cache be disabled at all? Or > is it just not possible (or complex) while running with I-Cache > enabled? you can only configure the "Cache Coherency Algorithm" in Coprocessor 0 Config register. This setting affects I-Cache and D-Cache at once. Maybe a workaround for icache_[en|dis]able could be to shift the instruction pointer from KSEG0 to KSEG1. This is the same principle you had with ddr_calibrate() in your first iteration of MT76xx patch series. > > > I could add them as dummy functions or with the same > > implementation as dcache_* > > That's perhaps a pragmatic work-around - if the I-Cache can't be > disabled at all. > > Thanks, > Stefan -- - Daniel