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From: Karl Beldan <karl.beldan@gmail.com>
Date: Thu, 20 Jul 2017 20:25:14 +0000
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Subject: Re: [RFC PATCH 0/2] Cavium NAND flash driver
To: Jan Glauber <jglauber@cavium.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>,
 Richard Weinberger <richard@nod.at>,
 David Woodhouse <dwmw2@infradead.org>,
 Brian Norris <computersforpeace@gmail.com>,
 Marek Vasut <marek.vasut@gmail.com>,
 Cyrille Pitchen <cyrille.pitchen@atmel.com>,
 "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>
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Hi,

On Mon, Mar 27, 2017 at 4:05 PM, Jan Glauber <jglauber@cavium.com> wrote:
> This series adds a driver for the nand flash controller as found on Cavium's
> ARM64 SOCs. For details about the controller see description of patch #2.
>
> The nand flash chip on the board I used for testing is:
>
> [   12.775877] nand: device found, Manufacturer ID: 0xc2, Chip ID: 0xf1
> [   12.782242] nand: Macronix MX30LF1GE8AB
> [   12.786072] nand: 128 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
>
> This chip has internal on-die ECC (which cannot be disabled). Data
> sheet can be found here:
> http://www.macronix.com/en-us/products/NAND-Flash/SLC-NAND-Flash/Pages/spec.aspx?p=MX30LF1GE8AB
>

I have some prototypes with this nand at hand.
I wonder if anybody could get their hands on more information than
what's on the datasheet or the archives on the site ?
On the site are available:
- a lld zip (low level driver) (no ondie ECC)
- a verilog zip (only ondie ECC timings simulation)
- a datasheet pdf (ambiguous, among other things ECC status vs sub pages)


Karl