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* [PATCH libdrm 1/3] headers: sync amdgpu_drm.h from airlied/drm-next
@ 2017-04-03  8:27 Nicolai Hähnle
       [not found] ` <20170403082720.13166-1-nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  0 siblings, 1 reply; 6+ messages in thread
From: Nicolai Hähnle @ 2017-04-03  8:27 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Nicolai Hähnle, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

From: Nicolai Hähnle <nicolai.haehnle@amd.com>

Changes include: PRT and preemption flags, sensor info, and some more
changes for Vega10.

Generated using make headers_install from airlied/drm-next commit
320d8c3d38739fa8e31a076b86cbdafcf8897d5e.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
---
 include/drm/amdgpu_drm.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index fa56499..516a9f2 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -225,20 +225,21 @@ struct drm_amdgpu_gem_userptr {
 #define AMDGPU_TILING_BANK_HEIGHT_MASK			0x3
 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT		19
 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK		0x3
 #define AMDGPU_TILING_NUM_BANKS_SHIFT			21
 #define AMDGPU_TILING_NUM_BANKS_MASK			0x3
 
 /* GFX9 and later: */
 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT		0
 #define AMDGPU_TILING_SWIZZLE_MODE_MASK			0x1f
 
+/* Set/Get helpers for tiling flags. */
 #define AMDGPU_TILING_SET(field, value) \
 	(((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
 #define AMDGPU_TILING_GET(value, field) \
 	(((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
 
 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
 
 /** The same structure is shared for input/output */
 struct drm_amdgpu_gem_metadata {
@@ -348,31 +349,47 @@ struct drm_amdgpu_gem_op {
 	/** GEM object handle */
 	__u32	handle;
 	/** AMDGPU_GEM_OP_* */
 	__u32	op;
 	/** Input or return value */
 	__u64	value;
 };
 
 #define AMDGPU_VA_OP_MAP			1
 #define AMDGPU_VA_OP_UNMAP			2
+#define AMDGPU_VA_OP_CLEAR			3
+#define AMDGPU_VA_OP_REPLACE			4
 
 /* Delay the page table update till the next CS */
 #define AMDGPU_VM_DELAY_UPDATE		(1 << 0)
 
 /* Mapping flags */
 /* readable mapping */
 #define AMDGPU_VM_PAGE_READABLE		(1 << 1)
 /* writable mapping */
 #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
 /* executable mapping, new for VI */
 #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
+/* partially resident texture */
+#define AMDGPU_VM_PAGE_PRT		(1 << 4)
+/* MTYPE flags use bit 5 to 8 */
+#define AMDGPU_VM_MTYPE_MASK		(0xf << 5)
+/* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
+#define AMDGPU_VM_MTYPE_DEFAULT		(0 << 5)
+/* Use NC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_NC		(1 << 5)
+/* Use WC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_WC		(2 << 5)
+/* Use CC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_CC		(3 << 5)
+/* Use UC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_UC		(4 << 5)
 
 struct drm_amdgpu_gem_va {
 	/** GEM object handle */
 	__u32 handle;
 	__u32 _pad;
 	/** AMDGPU_VA_OP_* */
 	__u32 operation;
 	/** AMDGPU_VM_PAGE_* */
 	__u32 flags;
 	/** va address to assign . Must be correctly aligned.*/
@@ -421,23 +438,26 @@ struct drm_amdgpu_cs_out {
 union drm_amdgpu_cs {
 	struct drm_amdgpu_cs_in in;
 	struct drm_amdgpu_cs_out out;
 };
 
 /* Specify flags to be used for IB */
 
 /* This IB should be submitted to CE */
 #define AMDGPU_IB_FLAG_CE	(1<<0)
 
-/* CE Preamble */
+/* Preamble flag, which means the IB could be dropped if no context switch */
 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
 
+/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
+#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
+
 struct drm_amdgpu_cs_chunk_ib {
 	__u32 _pad;
 	/** AMDGPU_IB_FLAG_* */
 	__u32 flags;
 	/** Virtual address to begin IB execution */
 	__u64 va_start;
 	/** Size of submission */
 	__u32 ib_bytes;
 	/** HW IP to submit to */
 	__u32 ip_type;
@@ -499,20 +519,24 @@ struct drm_amdgpu_cs_chunk_data {
 	/* Subquery id: Query GFX CE firmware version */
 	#define AMDGPU_INFO_FW_GFX_CE		0x06
 	/* Subquery id: Query GFX RLC firmware version */
 	#define AMDGPU_INFO_FW_GFX_RLC		0x07
 	/* Subquery id: Query GFX MEC firmware version */
 	#define AMDGPU_INFO_FW_GFX_MEC		0x08
 	/* Subquery id: Query SMC firmware version */
 	#define AMDGPU_INFO_FW_SMC		0x0a
 	/* Subquery id: Query SDMA firmware version */
 	#define AMDGPU_INFO_FW_SDMA		0x0b
+	/* Subquery id: Query PSP SOS firmware version */
+	#define AMDGPU_INFO_FW_SOS		0x0c
+	/* Subquery id: Query PSP ASD firmware version */
+	#define AMDGPU_INFO_FW_ASD		0x0d
 /* number of bytes moved for TTM migration */
 #define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
 /* the used VRAM size */
 #define AMDGPU_INFO_VRAM_USAGE			0x10
 /* the used GTT size */
 #define AMDGPU_INFO_GTT_USAGE			0x11
 /* Information about GDS, etc. resource configuration */
 #define AMDGPU_INFO_GDS_CONFIG			0x13
 /* Query information about VRAM and GTT domains */
 #define AMDGPU_INFO_VRAM_GTT			0x14
@@ -529,20 +553,36 @@ struct drm_amdgpu_cs_chunk_data {
 /* Query vce clock table */
 #define AMDGPU_INFO_VCE_CLOCK_TABLE		0x1A
 /* Query vbios related information */
 #define AMDGPU_INFO_VBIOS			0x1B
 	/* Subquery id: Query vbios size */
 	#define AMDGPU_INFO_VBIOS_SIZE		0x1
 	/* Subquery id: Query vbios image */
 	#define AMDGPU_INFO_VBIOS_IMAGE		0x2
 /* Query UVD handles */
 #define AMDGPU_INFO_NUM_HANDLES			0x1C
+/* Query sensor related information */
+#define AMDGPU_INFO_SENSOR			0x1D
+	/* Subquery id: Query GPU shader clock */
+	#define AMDGPU_INFO_SENSOR_GFX_SCLK		0x1
+	/* Subquery id: Query GPU memory clock */
+	#define AMDGPU_INFO_SENSOR_GFX_MCLK		0x2
+	/* Subquery id: Query GPU temperature */
+	#define AMDGPU_INFO_SENSOR_GPU_TEMP		0x3
+	/* Subquery id: Query GPU load */
+	#define AMDGPU_INFO_SENSOR_GPU_LOAD		0x4
+	/* Subquery id: Query average GPU power	*/
+	#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER	0x5
+	/* Subquery id: Query northbridge voltage */
+	#define AMDGPU_INFO_SENSOR_VDDNB		0x6
+	/* Subquery id: Query graphics voltage */
+	#define AMDGPU_INFO_SENSOR_VDDGFX		0x7
 
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT	8
 #define AMDGPU_INFO_MMR_SH_INDEX_MASK	0xff
 
 struct drm_amdgpu_query_fw {
 	/** AMDGPU_INFO_FW_* */
 	__u32 fw_type;
 	/**
@@ -592,20 +632,24 @@ struct drm_amdgpu_info {
 			/** For future use, no flags defined so far */
 			__u32 flags;
 		} read_mmr_reg;
 
 		struct drm_amdgpu_query_fw query_fw;
 
 		struct {
 			__u32 type;
 			__u32 offset;
 		} vbios_info;
+
+		struct {
+			__u32 type;
+		} sensor_info;
 	};
 };
 
 struct drm_amdgpu_info_gds {
 	/** GDS GFX partition size */
 	__u32 gds_gfx_partition_size;
 	/** GDS compute partition size */
 	__u32 compute_partition_size;
 	/** total GDS memory size */
 	__u32 gds_total_size;
@@ -703,20 +747,30 @@ struct drm_amdgpu_info_device {
 	__u32 pte_fragment_size;
 	__u32 gart_page_size;
 	/** constant engine ram size*/
 	__u32 ce_ram_size;
 	/** video memory type info*/
 	__u32 vram_type;
 	/** video memory bit width*/
 	__u32 vram_bit_width;
 	/* vce harvesting instance */
 	__u32 vce_harvest_config;
+	/* gfx double offchip LDS buffers */
+	__u32 gc_double_offchip_lds_buf;
+	/* NGG Primitive Buffer */
+	__u64 prim_buf_gpu_addr;
+	/* NGG Position Buffer */
+	__u64 pos_buf_gpu_addr;
+	/* NGG Control Sideband */
+	__u64 cntl_sb_buf_gpu_addr;
+	/* NGG Parameter Cache */
+	__u64 param_buf_gpu_addr;
 };
 
 struct drm_amdgpu_info_hw_ip {
 	/** Version of h/w IP */
 	__u32  hw_ip_version_major;
 	__u32  hw_ip_version_minor;
 	/** Capabilities */
 	__u64  capabilities_flags;
 	/** command buffer address start alignment*/
 	__u32  ib_start_alignment;
-- 
2.9.3

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH libdrm 2/3] headers: the uint*_t vs. __u* discrepancy in amdgpu_drm is fixed
       [not found] ` <20170403082720.13166-1-nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2017-04-03  8:27   ` Nicolai Hähnle
  2017-04-03  8:27   ` [PATCH libdrm 3/3] amdgpu: add REPLACE and CLEAR checking for VA op (v2) Nicolai Hähnle
  2017-04-03  9:36   ` [PATCH libdrm 1/3] headers: sync amdgpu_drm.h from airlied/drm-next Samuel Pitoiset
  2 siblings, 0 replies; 6+ messages in thread
From: Nicolai Hähnle @ 2017-04-03  8:27 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Nicolai Hähnle, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

From: Nicolai Hähnle <nicolai.haehnle@amd.com>

This was already done in commit 3dc002df3e5 ("amdgpu: sync amdgpu_drm.h
with kernel 4.11-rc2"), now update the README accordingly.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
---
 include/drm/README | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/include/drm/README b/include/drm/README
index f3cdf5d..870b0b5 100644
--- a/include/drm/README
+++ b/include/drm/README
@@ -89,24 +89,20 @@ have relative to their kernel equivalent.
 Nearly all headers:
  - Missing extern C notation.
 Status: Trivial.
 
 Most UMS headers:
  - Not using fixed size integers - compat ioctls are broken.
 Status: ?
 Promote to fixed size ints, which match the current (32bit) ones.
 
 
-amdgpu_drm.h
- - Using the stdint.h uint*_t over the respective __u* ones
-Status: Trivial.
-
 drm_mode.h
  - Missing DPI encode/connector pair.
 Status: Trivial.
 
 i915_drm.h
  - Missing PARAMS - HAS_POOLED_EU, MIN_EU_IN_POOL CONTEXT_PARAM_NO_ERROR_CAPTURE
 Status: Trivial.
 
 mga_drm.h
  - Typo fix, use struct over typedef.
-- 
2.9.3

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH libdrm 3/3] amdgpu: add REPLACE and CLEAR checking for VA op (v2)
       [not found] ` <20170403082720.13166-1-nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2017-04-03  8:27   ` [PATCH libdrm 2/3] headers: the uint*_t vs. __u* discrepancy in amdgpu_drm is fixed Nicolai Hähnle
@ 2017-04-03  8:27   ` Nicolai Hähnle
       [not found]     ` <20170403082720.13166-3-nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2017-04-03  9:36   ` [PATCH libdrm 1/3] headers: sync amdgpu_drm.h from airlied/drm-next Samuel Pitoiset
  2 siblings, 1 reply; 6+ messages in thread
From: Nicolai Hähnle @ 2017-04-03  8:27 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Junwei Zhang, Nicolai Hähnle,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

From: Junwei Zhang <Jerry.Zhang@amd.com>

v2: fix indent

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
---
 amdgpu/amdgpu_bo.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index f725bfd..8bc1ebd 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -696,21 +696,23 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
 			amdgpu_bo_handle bo,
 			uint64_t offset,
 			uint64_t size,
 			uint64_t addr,
 			uint64_t flags,
 			uint32_t ops)
 {
 	struct drm_amdgpu_gem_va va;
 	int r;
 
-	if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP)
+	if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP &&
+	    ops != AMDGPU_VA_OP_REPLACE && ops != AMDGPU_VA_OP_CLEAR)
+
 		return -EINVAL;
 
 	memset(&va, 0, sizeof(va));
 	va.handle = bo ? bo->handle : 0;
 	va.operation = ops;
 	va.flags = flags;
 	va.va_address = addr;
 	va.offset_in_bo = offset;
 	va.map_size = size;
 
-- 
2.9.3

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH libdrm 1/3] headers: sync amdgpu_drm.h from airlied/drm-next
       [not found] ` <20170403082720.13166-1-nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2017-04-03  8:27   ` [PATCH libdrm 2/3] headers: the uint*_t vs. __u* discrepancy in amdgpu_drm is fixed Nicolai Hähnle
  2017-04-03  8:27   ` [PATCH libdrm 3/3] amdgpu: add REPLACE and CLEAR checking for VA op (v2) Nicolai Hähnle
@ 2017-04-03  9:36   ` Samuel Pitoiset
  2 siblings, 0 replies; 6+ messages in thread
From: Samuel Pitoiset @ 2017-04-03  9:36 UTC (permalink / raw)
  To: Nicolai Hähnle, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Nicolai Hähnle



On 04/03/2017 10:27 AM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle <nicolai.haehnle@amd.com>
>
> Changes include: PRT and preemption flags, sensor info, and some more
> changes for Vega10.

Cool, thanks. I will be able to re-send the sensor info series for mesa. :)

>
> Generated using make headers_install from airlied/drm-next commit
> 320d8c3d38739fa8e31a076b86cbdafcf8897d5e.
>
> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
> ---
>  include/drm/amdgpu_drm.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
> index fa56499..516a9f2 100644
> --- a/include/drm/amdgpu_drm.h
> +++ b/include/drm/amdgpu_drm.h
> @@ -225,20 +225,21 @@ struct drm_amdgpu_gem_userptr {
>  #define AMDGPU_TILING_BANK_HEIGHT_MASK			0x3
>  #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT		19
>  #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK		0x3
>  #define AMDGPU_TILING_NUM_BANKS_SHIFT			21
>  #define AMDGPU_TILING_NUM_BANKS_MASK			0x3
>
>  /* GFX9 and later: */
>  #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT		0
>  #define AMDGPU_TILING_SWIZZLE_MODE_MASK			0x1f
>
> +/* Set/Get helpers for tiling flags. */
>  #define AMDGPU_TILING_SET(field, value) \
>  	(((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
>  #define AMDGPU_TILING_GET(value, field) \
>  	(((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
>
>  #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
>  #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
>
>  /** The same structure is shared for input/output */
>  struct drm_amdgpu_gem_metadata {
> @@ -348,31 +349,47 @@ struct drm_amdgpu_gem_op {
>  	/** GEM object handle */
>  	__u32	handle;
>  	/** AMDGPU_GEM_OP_* */
>  	__u32	op;
>  	/** Input or return value */
>  	__u64	value;
>  };
>
>  #define AMDGPU_VA_OP_MAP			1
>  #define AMDGPU_VA_OP_UNMAP			2
> +#define AMDGPU_VA_OP_CLEAR			3
> +#define AMDGPU_VA_OP_REPLACE			4
>
>  /* Delay the page table update till the next CS */
>  #define AMDGPU_VM_DELAY_UPDATE		(1 << 0)
>
>  /* Mapping flags */
>  /* readable mapping */
>  #define AMDGPU_VM_PAGE_READABLE		(1 << 1)
>  /* writable mapping */
>  #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
>  /* executable mapping, new for VI */
>  #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
> +/* partially resident texture */
> +#define AMDGPU_VM_PAGE_PRT		(1 << 4)
> +/* MTYPE flags use bit 5 to 8 */
> +#define AMDGPU_VM_MTYPE_MASK		(0xf << 5)
> +/* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
> +#define AMDGPU_VM_MTYPE_DEFAULT		(0 << 5)
> +/* Use NC MTYPE instead of default MTYPE */
> +#define AMDGPU_VM_MTYPE_NC		(1 << 5)
> +/* Use WC MTYPE instead of default MTYPE */
> +#define AMDGPU_VM_MTYPE_WC		(2 << 5)
> +/* Use CC MTYPE instead of default MTYPE */
> +#define AMDGPU_VM_MTYPE_CC		(3 << 5)
> +/* Use UC MTYPE instead of default MTYPE */
> +#define AMDGPU_VM_MTYPE_UC		(4 << 5)
>
>  struct drm_amdgpu_gem_va {
>  	/** GEM object handle */
>  	__u32 handle;
>  	__u32 _pad;
>  	/** AMDGPU_VA_OP_* */
>  	__u32 operation;
>  	/** AMDGPU_VM_PAGE_* */
>  	__u32 flags;
>  	/** va address to assign . Must be correctly aligned.*/
> @@ -421,23 +438,26 @@ struct drm_amdgpu_cs_out {
>  union drm_amdgpu_cs {
>  	struct drm_amdgpu_cs_in in;
>  	struct drm_amdgpu_cs_out out;
>  };
>
>  /* Specify flags to be used for IB */
>
>  /* This IB should be submitted to CE */
>  #define AMDGPU_IB_FLAG_CE	(1<<0)
>
> -/* CE Preamble */
> +/* Preamble flag, which means the IB could be dropped if no context switch */
>  #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
>
> +/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
> +#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
> +
>  struct drm_amdgpu_cs_chunk_ib {
>  	__u32 _pad;
>  	/** AMDGPU_IB_FLAG_* */
>  	__u32 flags;
>  	/** Virtual address to begin IB execution */
>  	__u64 va_start;
>  	/** Size of submission */
>  	__u32 ib_bytes;
>  	/** HW IP to submit to */
>  	__u32 ip_type;
> @@ -499,20 +519,24 @@ struct drm_amdgpu_cs_chunk_data {
>  	/* Subquery id: Query GFX CE firmware version */
>  	#define AMDGPU_INFO_FW_GFX_CE		0x06
>  	/* Subquery id: Query GFX RLC firmware version */
>  	#define AMDGPU_INFO_FW_GFX_RLC		0x07
>  	/* Subquery id: Query GFX MEC firmware version */
>  	#define AMDGPU_INFO_FW_GFX_MEC		0x08
>  	/* Subquery id: Query SMC firmware version */
>  	#define AMDGPU_INFO_FW_SMC		0x0a
>  	/* Subquery id: Query SDMA firmware version */
>  	#define AMDGPU_INFO_FW_SDMA		0x0b
> +	/* Subquery id: Query PSP SOS firmware version */
> +	#define AMDGPU_INFO_FW_SOS		0x0c
> +	/* Subquery id: Query PSP ASD firmware version */
> +	#define AMDGPU_INFO_FW_ASD		0x0d
>  /* number of bytes moved for TTM migration */
>  #define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
>  /* the used VRAM size */
>  #define AMDGPU_INFO_VRAM_USAGE			0x10
>  /* the used GTT size */
>  #define AMDGPU_INFO_GTT_USAGE			0x11
>  /* Information about GDS, etc. resource configuration */
>  #define AMDGPU_INFO_GDS_CONFIG			0x13
>  /* Query information about VRAM and GTT domains */
>  #define AMDGPU_INFO_VRAM_GTT			0x14
> @@ -529,20 +553,36 @@ struct drm_amdgpu_cs_chunk_data {
>  /* Query vce clock table */
>  #define AMDGPU_INFO_VCE_CLOCK_TABLE		0x1A
>  /* Query vbios related information */
>  #define AMDGPU_INFO_VBIOS			0x1B
>  	/* Subquery id: Query vbios size */
>  	#define AMDGPU_INFO_VBIOS_SIZE		0x1
>  	/* Subquery id: Query vbios image */
>  	#define AMDGPU_INFO_VBIOS_IMAGE		0x2
>  /* Query UVD handles */
>  #define AMDGPU_INFO_NUM_HANDLES			0x1C
> +/* Query sensor related information */
> +#define AMDGPU_INFO_SENSOR			0x1D
> +	/* Subquery id: Query GPU shader clock */
> +	#define AMDGPU_INFO_SENSOR_GFX_SCLK		0x1
> +	/* Subquery id: Query GPU memory clock */
> +	#define AMDGPU_INFO_SENSOR_GFX_MCLK		0x2
> +	/* Subquery id: Query GPU temperature */
> +	#define AMDGPU_INFO_SENSOR_GPU_TEMP		0x3
> +	/* Subquery id: Query GPU load */
> +	#define AMDGPU_INFO_SENSOR_GPU_LOAD		0x4
> +	/* Subquery id: Query average GPU power	*/
> +	#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER	0x5
> +	/* Subquery id: Query northbridge voltage */
> +	#define AMDGPU_INFO_SENSOR_VDDNB		0x6
> +	/* Subquery id: Query graphics voltage */
> +	#define AMDGPU_INFO_SENSOR_VDDGFX		0x7
>
>  #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
>  #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
>  #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT	8
>  #define AMDGPU_INFO_MMR_SH_INDEX_MASK	0xff
>
>  struct drm_amdgpu_query_fw {
>  	/** AMDGPU_INFO_FW_* */
>  	__u32 fw_type;
>  	/**
> @@ -592,20 +632,24 @@ struct drm_amdgpu_info {
>  			/** For future use, no flags defined so far */
>  			__u32 flags;
>  		} read_mmr_reg;
>
>  		struct drm_amdgpu_query_fw query_fw;
>
>  		struct {
>  			__u32 type;
>  			__u32 offset;
>  		} vbios_info;
> +
> +		struct {
> +			__u32 type;
> +		} sensor_info;
>  	};
>  };
>
>  struct drm_amdgpu_info_gds {
>  	/** GDS GFX partition size */
>  	__u32 gds_gfx_partition_size;
>  	/** GDS compute partition size */
>  	__u32 compute_partition_size;
>  	/** total GDS memory size */
>  	__u32 gds_total_size;
> @@ -703,20 +747,30 @@ struct drm_amdgpu_info_device {
>  	__u32 pte_fragment_size;
>  	__u32 gart_page_size;
>  	/** constant engine ram size*/
>  	__u32 ce_ram_size;
>  	/** video memory type info*/
>  	__u32 vram_type;
>  	/** video memory bit width*/
>  	__u32 vram_bit_width;
>  	/* vce harvesting instance */
>  	__u32 vce_harvest_config;
> +	/* gfx double offchip LDS buffers */
> +	__u32 gc_double_offchip_lds_buf;
> +	/* NGG Primitive Buffer */
> +	__u64 prim_buf_gpu_addr;
> +	/* NGG Position Buffer */
> +	__u64 pos_buf_gpu_addr;
> +	/* NGG Control Sideband */
> +	__u64 cntl_sb_buf_gpu_addr;
> +	/* NGG Parameter Cache */
> +	__u64 param_buf_gpu_addr;
>  };
>
>  struct drm_amdgpu_info_hw_ip {
>  	/** Version of h/w IP */
>  	__u32  hw_ip_version_major;
>  	__u32  hw_ip_version_minor;
>  	/** Capabilities */
>  	__u64  capabilities_flags;
>  	/** command buffer address start alignment*/
>  	__u32  ib_start_alignment;
>
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^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH libdrm 3/3] amdgpu: add REPLACE and CLEAR checking for VA op (v2)
       [not found]     ` <20170403082720.13166-3-nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2017-04-03 10:54       ` Marek Olšák
       [not found]         ` <CAAxE2A5SZ93EoQ=hhu6oZj8ZfSNEZ5+NvZzRZzJYCONj7AW+8Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
  0 siblings, 1 reply; 6+ messages in thread
From: Marek Olšák @ 2017-04-03 10:54 UTC (permalink / raw)
  To: Nicolai Hähnle
  Cc: Junwei Zhang, dri-devel, Nicolai Hähnle, amd-gfx mailing list

On Mon, Apr 3, 2017 at 10:27 AM, Nicolai Hähnle <nhaehnle@gmail.com> wrote:
> From: Junwei Zhang <Jerry.Zhang@amd.com>
>
> v2: fix indent
>
> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
> Reviewed-by: Christian König <christian.koenig@amd.com>
> ---
>  amdgpu/amdgpu_bo.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
> index f725bfd..8bc1ebd 100644
> --- a/amdgpu/amdgpu_bo.c
> +++ b/amdgpu/amdgpu_bo.c
> @@ -696,21 +696,23 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
>                         amdgpu_bo_handle bo,
>                         uint64_t offset,
>                         uint64_t size,
>                         uint64_t addr,
>                         uint64_t flags,
>                         uint32_t ops)
>  {
>         struct drm_amdgpu_gem_va va;
>         int r;
>
> -       if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP)
> +       if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP &&
> +           ops != AMDGPU_VA_OP_REPLACE && ops != AMDGPU_VA_OP_CLEAR)
> +

Spurious empty line?

Other than that, the series is:
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

I don't know how Dave feels about pushing this into libdrm when it's
not in Linus's tree.

Marek
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^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH libdrm 3/3] amdgpu: add REPLACE and CLEAR checking for VA op (v2)
       [not found]         ` <CAAxE2A5SZ93EoQ=hhu6oZj8ZfSNEZ5+NvZzRZzJYCONj7AW+8Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2017-04-03 16:16           ` Emil Velikov
  0 siblings, 0 replies; 6+ messages in thread
From: Emil Velikov @ 2017-04-03 16:16 UTC (permalink / raw)
  To: Marek Olšák
  Cc: Junwei Zhang, Nicolai Hähnle, amd-gfx mailing list,
	Nicolai Hähnle, dri-devel

On 3 April 2017 at 11:54, Marek Olšák <maraeo@gmail.com> wrote:
> On Mon, Apr 3, 2017 at 10:27 AM, Nicolai Hähnle <nhaehnle@gmail.com> wrote:
>> From: Junwei Zhang <Jerry.Zhang@amd.com>
>>
>> v2: fix indent
>>
>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
>> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
>> Reviewed-by: Christian König <christian.koenig@amd.com>
>> ---
>>  amdgpu/amdgpu_bo.c | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
>> index f725bfd..8bc1ebd 100644
>> --- a/amdgpu/amdgpu_bo.c
>> +++ b/amdgpu/amdgpu_bo.c
>> @@ -696,21 +696,23 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
>>                         amdgpu_bo_handle bo,
>>                         uint64_t offset,
>>                         uint64_t size,
>>                         uint64_t addr,
>>                         uint64_t flags,
>>                         uint32_t ops)
>>  {
>>         struct drm_amdgpu_gem_va va;
>>         int r;
>>
>> -       if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP)
>> +       if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP &&
>> +           ops != AMDGPU_VA_OP_REPLACE && ops != AMDGPU_VA_OP_CLEAR)
>> +
>
> Spurious empty line?
>
> Other than that, the series is:
> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
>
> I don't know how Dave feels about pushing this into libdrm when it's
> not in Linus's tree.
>
I'm not Dave, so pardon for dropping in.

AFAICT the idea is that once the feature is within a non-rebase branch
such as drm-next, it's part of the ABI. As such one can use it across
the board - be that in here, Mesa or elsewhere.

That said, the series looks great. Thanks for the updates gents.
Acked-by: Emil Velikov <emil.velikov@collabora.com>

Thanks
Emil
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^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2017-04-03 16:16 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-03  8:27 [PATCH libdrm 1/3] headers: sync amdgpu_drm.h from airlied/drm-next Nicolai Hähnle
     [not found] ` <20170403082720.13166-1-nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-04-03  8:27   ` [PATCH libdrm 2/3] headers: the uint*_t vs. __u* discrepancy in amdgpu_drm is fixed Nicolai Hähnle
2017-04-03  8:27   ` [PATCH libdrm 3/3] amdgpu: add REPLACE and CLEAR checking for VA op (v2) Nicolai Hähnle
     [not found]     ` <20170403082720.13166-3-nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-04-03 10:54       ` Marek Olšák
     [not found]         ` <CAAxE2A5SZ93EoQ=hhu6oZj8ZfSNEZ5+NvZzRZzJYCONj7AW+8Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-04-03 16:16           ` Emil Velikov
2017-04-03  9:36   ` [PATCH libdrm 1/3] headers: sync amdgpu_drm.h from airlied/drm-next Samuel Pitoiset

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