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From: Grant Likely <grant.likely@secretlab.ca>
Date: Mon, 19 Sep 2011 18:22:15 -0600
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Subject: Re: [PATCH 5/5] ARM: gic: add OF based initialization
To: Rob Herring <robherring2@gmail.com>
Cc: "Cousson, Benoit" <b-cousson@ti.com>,
        Thomas Abraham <thomas.abraham@linaro.org>,
        "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
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On Mon, Sep 19, 2011 at 3:53 PM, Rob Herring <robherring2@gmail.com> wrote:
> On 09/19/2011 04:14 PM, Grant Likely wrote:
>> * ARM Generic Interrupt Controller
>>
>> ARM SMP cores are often associated with a GIC, providing per processor
>> interrupts (PPI), shared processor interrupts (SPI) and software
>> generated interrupts (SGI).
>>
>> Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
>> Secondary GICs are cascaded into the upward interrupt controller and do not
>> have PPIs or SGIs.
>>
>> Main node required properties:
>>
>> - compatible : should be one of:
>>        "arm,cortex-a9-gic"
>>        "arm,arm11mp-gic"
>> - interrupt-controller : Identifies the node as an interrupt controller
>> - #interrupt-cells : Specifies the number of cells needed to encode an
>>   interrupt source.  The type shall be a <u32> and the value shall be 3.
>>
>>   The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
>> interrupts.
>>   The 2nd cell contains the interrupt number for the interrupt type.
>> SPI interrupts are in the range [0-987].  PPI interrupts are in the
>> range [0-15].
>>   The 3rd cell is the flags, encoded as follows:
>>         bits[3:0] trigger type and level flags.
>>                     1 = low-to-high edge triggered
>>                     2 = high-to-low edge triggered
>>                     4 = active high level-sensitive
>>                     8 = active low level-sensitive
>>         bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to
>> each of the 8 possible cpus attached to the GIC.  A bit set to '1'
>> indicated the interrupt is wired to that CPU.  Only valid for PPI
>> interrupts.
>>
> How about a cpu mask of 0 means SPI and non-zero means PPI? Then we can
> drop the first cell.

Cells are cheap, and it is better to be explicit.  It is certainly
easier to extend in the future too if the type cell is used.

g.

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
Subject: Re: [PATCH 5/5] ARM: gic: add OF based initialization
Date: Mon, 19 Sep 2011 18:22:15 -0600
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On Mon, Sep 19, 2011 at 3:53 PM, Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On 09/19/2011 04:14 PM, Grant Likely wrote:
>> * ARM Generic Interrupt Controller
>>
>> ARM SMP cores are often associated with a GIC, providing per processor
>> interrupts (PPI), shared processor interrupts (SPI) and software
>> generated interrupts (SGI).
>>
>> Primary GIC is attached directly to the CPU and typically has PPIs and S=
GIs.
>> Secondary GICs are cascaded into the upward interrupt controller and do =
not
>> have PPIs or SGIs.
>>
>> Main node required properties:
>>
>> - compatible : should be one of:
>> =A0 =A0 =A0 =A0"arm,cortex-a9-gic"
>> =A0 =A0 =A0 =A0"arm,arm11mp-gic"
>> - interrupt-controller : Identifies the node as an interrupt controller
>> - #interrupt-cells : Specifies the number of cells needed to encode an
>> =A0 interrupt source. =A0The type shall be a <u32> and the value shall b=
e 3.
>>
>> =A0 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
>> interrupts.
>> =A0 The 2nd cell contains the interrupt number for the interrupt type.
>> SPI interrupts are in the range [0-987]. =A0PPI interrupts are in the
>> range [0-15].
>> =A0 The 3rd cell is the flags, encoded as follows:
>> =A0 =A0 =A0 =A0 bits[3:0] trigger type and level flags.
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 1 =3D low-to-high edge triggered
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 2 =3D high-to-low edge triggered
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 4 =3D active high level-sensitive
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 8 =3D active low level-sensitive
>> =A0 =A0 =A0 =A0 bits[15:8] PPI interrupt cpu mask. =A0Each bit correspon=
ds to
>> each of the 8 possible cpus attached to the GIC. =A0A bit set to '1'
>> indicated the interrupt is wired to that CPU. =A0Only valid for PPI
>> interrupts.
>>
> How about a cpu mask of 0 means SPI and non-zero means PPI? Then we can
> drop the first cell.

Cells are cheap, and it is better to be explicit.  It is certainly
easier to extend in the future too if the type cell is used.

g.

From mboxrd@z Thu Jan  1 00:00:00 1970
From: grant.likely@secretlab.ca (Grant Likely)
Date: Mon, 19 Sep 2011 18:22:15 -0600
Subject: [PATCH 5/5] ARM: gic: add OF based initialization
In-Reply-To: <4E77B9E3.40004@gmail.com>
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	<4E71CE5D.9030900@ti.com> <4E71F978.6020402@gmail.com>
	<4E72030F.1090300@ti.com>
	<4E722B2D.4050307@gmail.com> <4E76615C.3000005@gmail.com>
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On Mon, Sep 19, 2011 at 3:53 PM, Rob Herring <robherring2@gmail.com> wrote:
> On 09/19/2011 04:14 PM, Grant Likely wrote:
>> * ARM Generic Interrupt Controller
>>
>> ARM SMP cores are often associated with a GIC, providing per processor
>> interrupts (PPI), shared processor interrupts (SPI) and software
>> generated interrupts (SGI).
>>
>> Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
>> Secondary GICs are cascaded into the upward interrupt controller and do not
>> have PPIs or SGIs.
>>
>> Main node required properties:
>>
>> - compatible : should be one of:
>> ? ? ? ?"arm,cortex-a9-gic"
>> ? ? ? ?"arm,arm11mp-gic"
>> - interrupt-controller : Identifies the node as an interrupt controller
>> - #interrupt-cells : Specifies the number of cells needed to encode an
>> ? interrupt source. ?The type shall be a <u32> and the value shall be 3.
>>
>> ? The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
>> interrupts.
>> ? The 2nd cell contains the interrupt number for the interrupt type.
>> SPI interrupts are in the range [0-987]. ?PPI interrupts are in the
>> range [0-15].
>> ? The 3rd cell is the flags, encoded as follows:
>> ? ? ? ? bits[3:0] trigger type and level flags.
>> ? ? ? ? ? ? ? ? ? ? 1 = low-to-high edge triggered
>> ? ? ? ? ? ? ? ? ? ? 2 = high-to-low edge triggered
>> ? ? ? ? ? ? ? ? ? ? 4 = active high level-sensitive
>> ? ? ? ? ? ? ? ? ? ? 8 = active low level-sensitive
>> ? ? ? ? bits[15:8] PPI interrupt cpu mask. ?Each bit corresponds to
>> each of the 8 possible cpus attached to the GIC. ?A bit set to '1'
>> indicated the interrupt is wired to that CPU. ?Only valid for PPI
>> interrupts.
>>
> How about a cpu mask of 0 means SPI and non-zero means PPI? Then we can
> drop the first cell.

Cells are cheap, and it is better to be explicit.  It is certainly
easier to extend in the future too if the type cell is used.

g.