From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Date: Tue, 16 Jun 2015 01:00:40 +0530 Subject: [U-Boot] [PATCH 0/6] spi: cadence_qspi: optimize & fix indirect read-writes In-Reply-To: <9026814FBF99304F9FA3AC3FB72F3E2F016A85A2@SAFEX1MAIL4.st.com> References: <1434392374-28193-1-git-send-email-vikas.manocha@st.com> <9026814FBF99304F9FA3AC3FB72F3E2F016A85A2@SAFEX1MAIL4.st.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 16 June 2015 at 00:21, Vikas MANOCHA wrote: > Hello All, > > I just figured out that this patchset has dependency on another patchset under review. I am not sure how to handle situations like this. > I can think of following options, please let me know if anyone of these is ok: > > - I send the next version of my previous patchset (under review) with addition of this patchset. With it, all the patches will apply on master. > - wait for the previous patchset to get in mainline....(might take some time). Just create the patches on top of master[1] and add the subject-prefix as PATCH RESEND. Pls- try to work on master always for avoiding dependencies. [1] http://git.denx.de/?p=u-boot.git;a=summary > > Rgds, > Vikas > >> -----Original Message----- >> From: Vikas MANOCHA >> Sent: Monday, June 15, 2015 11:19 AM >> To: u-boot at lists.denx.de; sr at denx.de; grmoore at opensource.altera.com; >> dinguyen at opensource.altera.com >> Cc: Vikas MANOCHA >> Subject: [PATCH 0/6] spi: cadence_qspi: optimize & fix indirect read-writes >> >> This patchset: >> - removes sram polling while reading/writing from flash. >> - fixes trigger base & transfer start address register programming. This fix >> superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb >> trigger address setting" >> - adds support to get fifo width from device tree >> >> Vikas Manocha (6): >> spi: cadence_qspi: remove sram polling from flash read >> spi: cadence_qspi: remove sram polling from flash write >> spi: cadence_qspi: move trigger base configuration in init >> spi: cadence_qspi: fix indirect read/write start address >> spi: cadence_qspi: fix base trigger address & transfer start address >> spi: cadence_qspi: get fifo width from device tree >> >> arch/arm/dts/socfpga.dtsi | 2 + >> arch/arm/dts/stv0991.dts | 4 +- >> drivers/spi/cadence_qspi.c | 14 +++-- >> drivers/spi/cadence_qspi.h | 6 +- >> drivers/spi/cadence_qspi_apb.c | 124 +++++++++------------------------------- >> 5 files changed, 43 insertions(+), 107 deletions(-) thanks! -- Jagan | Openedev.