From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: MIME-Version: 1.0 In-Reply-To: <20180831191225.GA43106@bhelgaas-glaptop.roam.corp.google.com> References: <20180831073057.14626-1-drake@endlessm.com> <20180831191225.GA43106@bhelgaas-glaptop.roam.corp.google.com> From: Daniel Drake Date: Mon, 3 Sep 2018 16:56:32 +0800 Message-ID: Subject: Re: [PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues To: Bjorn Helgaas Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, Linux Upstreaming Team , nouveau@lists.freedesktop.org, Linux PM , Peter Wu , kherbst@redhat.com, Andy Shevchenko , "Rafael J. Wysocki" , Keith Busch , Mika Westerberg , Jon Derrick Content-Type: text/plain; charset="UTF-8" List-ID: On Sat, Sep 1, 2018 at 3:12 AM, Bjorn Helgaas wrote: > If true, this sounds like some sort of erratum, so it would be good to > get some input from Intel, and I cc'd a few Intel folks. Yes, it would be great to get their input. > It's interesting that all the systems below are from Asus. That makes > me think there's some BIOS or SMM connection, e.g., SMM traps the > register write and does something magic. Is there a way I can check if there is a SMM trap active for this address? > Does this problem happen after a full system suspend/resume, or does > it happen after runtime suspend of only the GPU? Or runtime suspend > of only the GPU and the upstream bridge? runtime suspend/resume works fine. It only happens after S3 suspend. > Can we tell whether Windows rewrites this register unconditionally at > resume-time? If so, it may be more robust for Linux to do the same. > The whole thing is black magic, which I hate, but if it's our only > choice, it may be better to have this applied everywhere so we don't > keep stubbing our toes on new systems that require the quirk. Any suggestions for how to make this happen? Booting windows in virt-manager (hoping that I could then spy on PCI config space reg accesses), I don't see an option for S3 suspend, but I'll keep looking into this. Thanks Daniel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Drake Subject: Re: [PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues Date: Mon, 3 Sep 2018 16:56:32 +0800 Message-ID: References: <20180831073057.14626-1-drake@endlessm.com> <20180831191225.GA43106@bhelgaas-glaptop.roam.corp.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180831191225.GA43106-1RhO1Y9PlrlHTL0Zs8A6p5iNqAH0jzoTYJqu5kTmcBRl57MIdRCFDg@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Nouveau" To: Bjorn Helgaas Cc: Mika Westerberg , Linux PM , linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, "Rafael J. Wysocki" , Keith Busch , nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, Bjorn Helgaas , Andy Shevchenko , Linux Upstreaming Team , Jon Derrick List-Id: linux-pm@vger.kernel.org T24gU2F0LCBTZXAgMSwgMjAxOCBhdCAzOjEyIEFNLCBCam9ybiBIZWxnYWFzIDxoZWxnYWFzQGtl cm5lbC5vcmc+IHdyb3RlOgo+IElmIHRydWUsIHRoaXMgc291bmRzIGxpa2Ugc29tZSBzb3J0IG9m IGVycmF0dW0sIHNvIGl0IHdvdWxkIGJlIGdvb2QgdG8KPiBnZXQgc29tZSBpbnB1dCBmcm9tIElu dGVsLCBhbmQgSSBjYydkIGEgZmV3IEludGVsIGZvbGtzLgoKWWVzLCBpdCB3b3VsZCBiZSBncmVh dCB0byBnZXQgdGhlaXIgaW5wdXQuCgo+IEl0J3MgaW50ZXJlc3RpbmcgdGhhdCBhbGwgdGhlIHN5 c3RlbXMgYmVsb3cgYXJlIGZyb20gQXN1cy4gIFRoYXQgbWFrZXMKPiBtZSB0aGluayB0aGVyZSdz IHNvbWUgQklPUyBvciBTTU0gY29ubmVjdGlvbiwgZS5nLiwgU01NIHRyYXBzIHRoZQo+IHJlZ2lz dGVyIHdyaXRlIGFuZCBkb2VzIHNvbWV0aGluZyBtYWdpYy4KCklzIHRoZXJlIGEgd2F5IEkgY2Fu IGNoZWNrIGlmIHRoZXJlIGlzIGEgU01NIHRyYXAgYWN0aXZlIGZvciB0aGlzIGFkZHJlc3M/Cgo+ IERvZXMgdGhpcyBwcm9ibGVtIGhhcHBlbiBhZnRlciBhIGZ1bGwgc3lzdGVtIHN1c3BlbmQvcmVz dW1lLCBvciBkb2VzCj4gaXQgaGFwcGVuIGFmdGVyIHJ1bnRpbWUgc3VzcGVuZCBvZiBvbmx5IHRo ZSBHUFU/ICBPciBydW50aW1lIHN1c3BlbmQKPiBvZiBvbmx5IHRoZSBHUFUgYW5kIHRoZSB1cHN0 cmVhbSBicmlkZ2U/CgpydW50aW1lIHN1c3BlbmQvcmVzdW1lIHdvcmtzIGZpbmUuIEl0IG9ubHkg aGFwcGVucyBhZnRlciBTMyBzdXNwZW5kLgoKPiBDYW4gd2UgdGVsbCB3aGV0aGVyIFdpbmRvd3Mg cmV3cml0ZXMgdGhpcyByZWdpc3RlciB1bmNvbmRpdGlvbmFsbHkgYXQKPiByZXN1bWUtdGltZT8g IElmIHNvLCBpdCBtYXkgYmUgbW9yZSByb2J1c3QgZm9yIExpbnV4IHRvIGRvIHRoZSBzYW1lLgo+ IFRoZSB3aG9sZSB0aGluZyBpcyBibGFjayBtYWdpYywgd2hpY2ggSSBoYXRlLCBidXQgaWYgaXQn cyBvdXIgb25seQo+IGNob2ljZSwgaXQgbWF5IGJlIGJldHRlciB0byBoYXZlIHRoaXMgYXBwbGll ZCBldmVyeXdoZXJlIHNvIHdlIGRvbid0Cj4ga2VlcCBzdHViYmluZyBvdXIgdG9lcyBvbiBuZXcg c3lzdGVtcyB0aGF0IHJlcXVpcmUgdGhlIHF1aXJrLgoKQW55IHN1Z2dlc3Rpb25zIGZvciBob3cg dG8gbWFrZSB0aGlzIGhhcHBlbj8gQm9vdGluZyB3aW5kb3dzIGluCnZpcnQtbWFuYWdlciAoaG9w aW5nIHRoYXQgSSBjb3VsZCB0aGVuIHNweSBvbiBQQ0kgY29uZmlnIHNwYWNlIHJlZwphY2Nlc3Nl cyksIEkgZG9uJ3Qgc2VlIGFuIG9wdGlvbiBmb3IgUzMgc3VzcGVuZCwgYnV0IEknbGwga2VlcCBs b29raW5nCmludG8gdGhpcy4KClRoYW5rcwpEYW5pZWwKX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KTm91dmVhdSBtYWlsaW5nIGxpc3QKTm91dmVhdUBsaXN0 cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9s aXN0aW5mby9ub3V2ZWF1Cg==