From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753348AbeAaQxC (ORCPT ); Wed, 31 Jan 2018 11:53:02 -0500 Received: from mail-ua0-f180.google.com ([209.85.217.180]:35316 "EHLO mail-ua0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751842AbeAaQxB (ORCPT ); Wed, 31 Jan 2018 11:53:01 -0500 X-Google-Smtp-Source: AH8x22639tL9UuKdOwwiLz1nuY/EhUHoY7voi2fphj7R+zEfkDXUVkxfBIKFGz3hnZO0oA3/GLc0yCBhm3TZbfKL3l0= MIME-Version: 1.0 In-Reply-To: References: <20180130202913.28724-1-thierry.escande@collabora.com> <20180130202913.28724-34-thierry.escande@collabora.com> <1517403243.14302.1.camel@pengutronix.de> From: Doug Anderson Date: Wed, 31 Jan 2018 08:52:59 -0800 X-Google-Sender-Auth: o5ocRZlgLtz0ByLp4uYQFsxc3LQ Message-ID: Subject: Re: [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31 To: Sean Paul Cc: Lucas Stach , Thierry Escande , Archit Taneja , Inki Dae , Thierry Reding , Sandy Huang , David Airlie , Tomasz Figa , Enric Balletbo i Serra , Zain Wang , Lin Huang , dri-devel , Linux Kernel Mailing List , "open list:ARM/Rockchip SoC..." , Yakir Yang , =?UTF-8?Q?=C3=98rjan_Eide?= , Mark Yao , Haixia Shi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Wed, Jan 31, 2018 at 7:16 AM, Sean Paul wrote: > On Wed, Jan 31, 2018 at 7:54 AM, Lucas Stach wrote: >> Am Dienstag, den 30.01.2018, 21:29 +0100 schrieb Thierry Escande: >>> From: Sean Paul >>> >>> Change the mode for Sharp lq123p1jx31 panel to something more >>> rockchip-friendly such that we can use the fixed PLLs to >>> generate the pixel clock >> >> This should really switch to a display timing instead of exposing a >> single mode. The display timing has min, typical, max tuples for all >> the timings values, which would allow the attached driver to vary the >> timings inside the allowed bounds if it makes sense. >> >> Trying to hit a specific pixel clock to free up a PLL is exactly one of >> the use cases envisioned for the display timings stuff. >> > > Agreed, I think we had this discussion the first time around. We > should drop this patch. > > Thanks for catching this! Are you sure we should drop this? In order for things to work properly (not generate noise on the digitizer or other EMI), this needs to run at a very specific pixel clock with very specific blanking times. I know that earlier we had slightly different blanking times and Samsung came back and said that there was noise on the digitizer. I could be wrong, but I don't think there's any way currently to be able to specify exactly what timings should be used on a particular board. Don't get be wrong--I think a patch such as this one that claims a single board's timings as the "right" ones for a generic panel is a bit of a hack. ...but at the same time there are no other users of this panel (that I know of) in mainline and the timings presented here are certainly sane timings for this panel. In any case, previous discussion at: https://patchwork.kernel.org/patch/9614603/ ...oh, and looking at the previous discussion reminds me that the timings presented in this here patch are actually not the right ones (they have the right PLL, but the wrong blankings to avoid the noise issues). See -Doug From mboxrd@z Thu Jan 1 00:00:00 1970 From: Doug Anderson Subject: Re: [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31 Date: Wed, 31 Jan 2018 08:52:59 -0800 Message-ID: References: <20180130202913.28724-1-thierry.escande@collabora.com> <20180130202913.28724-34-thierry.escande@collabora.com> <1517403243.14302.1.camel@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Sean Paul Cc: Haixia Shi , Thierry Escande , Lin Huang , David Airlie , Linux Kernel Mailing List , dri-devel , Tomasz Figa , "open list:ARM/Rockchip SoC..." , Thierry Reding , Yakir Yang , Enric Balletbo i Serra , =?UTF-8?Q?=C3=98rjan_Eide?= , Mark Yao , Zain Wang List-Id: linux-rockchip.vger.kernel.org SGksCgoKT24gV2VkLCBKYW4gMzEsIDIwMTggYXQgNzoxNiBBTSwgU2VhbiBQYXVsIDxzZWFucGF1 bEBjaHJvbWl1bS5vcmc+IHdyb3RlOgo+IE9uIFdlZCwgSmFuIDMxLCAyMDE4IGF0IDc6NTQgQU0s IEx1Y2FzIFN0YWNoIDxsLnN0YWNoQHBlbmd1dHJvbml4LmRlPiB3cm90ZToKPj4gQW0gRGllbnN0 YWcsIGRlbiAzMC4wMS4yMDE4LCAyMToyOSArMDEwMCBzY2hyaWViIFRoaWVycnkgRXNjYW5kZToK Pj4+IEZyb206IFNlYW4gUGF1bCA8c2VhbnBhdWxAY2hyb21pdW0ub3JnPgo+Pj4KPj4+IENoYW5n ZSB0aGUgbW9kZSBmb3IgU2hhcnAgbHExMjNwMWp4MzEgcGFuZWwgdG8gc29tZXRoaW5nIG1vcmUK Pj4+IHJvY2tjaGlwLWZyaWVuZGx5IHN1Y2ggdGhhdCB3ZSBjYW4gdXNlIHRoZSBmaXhlZCBQTExz IHRvCj4+PiBnZW5lcmF0ZSB0aGUgcGl4ZWwgY2xvY2sKPj4KPj4gVGhpcyBzaG91bGQgcmVhbGx5 IHN3aXRjaCB0byBhIGRpc3BsYXkgdGltaW5nIGluc3RlYWQgb2YgZXhwb3NpbmcgYQo+PiBzaW5n bGUgbW9kZS4gVGhlIGRpc3BsYXkgdGltaW5nIGhhcyBtaW4sIHR5cGljYWwsIG1heCB0dXBsZXMg Zm9yIGFsbAo+PiB0aGUgdGltaW5ncyB2YWx1ZXMsIHdoaWNoIHdvdWxkIGFsbG93IHRoZSBhdHRh Y2hlZCBkcml2ZXIgdG8gdmFyeSB0aGUKPj4gdGltaW5ncyBpbnNpZGUgdGhlIGFsbG93ZWQgYm91 bmRzIGlmIGl0IG1ha2VzIHNlbnNlLgo+Pgo+PiBUcnlpbmcgdG8gaGl0IGEgc3BlY2lmaWMgcGl4 ZWwgY2xvY2sgdG8gZnJlZSB1cCBhIFBMTCBpcyBleGFjdGx5IG9uZSBvZgo+PiB0aGUgdXNlIGNh c2VzIGVudmlzaW9uZWQgZm9yIHRoZSBkaXNwbGF5IHRpbWluZ3Mgc3R1ZmYuCj4+Cj4KPiBBZ3Jl ZWQsIEkgdGhpbmsgd2UgaGFkIHRoaXMgZGlzY3Vzc2lvbiB0aGUgZmlyc3QgdGltZSBhcm91bmQu IFdlCj4gc2hvdWxkIGRyb3AgdGhpcyBwYXRjaC4KPgo+IFRoYW5rcyBmb3IgY2F0Y2hpbmcgdGhp cyEKCkFyZSB5b3Ugc3VyZSB3ZSBzaG91bGQgZHJvcCB0aGlzPyAgSW4gb3JkZXIgZm9yIHRoaW5n cyB0byB3b3JrCnByb3Blcmx5IChub3QgZ2VuZXJhdGUgbm9pc2Ugb24gdGhlIGRpZ2l0aXplciBv ciBvdGhlciBFTUkpLCB0aGlzCm5lZWRzIHRvIHJ1biBhdCBhIHZlcnkgc3BlY2lmaWMgcGl4ZWwg Y2xvY2sgd2l0aCB2ZXJ5IHNwZWNpZmljCmJsYW5raW5nIHRpbWVzLiAgSSBrbm93IHRoYXQgZWFy bGllciB3ZSBoYWQgc2xpZ2h0bHkgZGlmZmVyZW50CmJsYW5raW5nIHRpbWVzIGFuZCBTYW1zdW5n IGNhbWUgYmFjayBhbmQgc2FpZCB0aGF0IHRoZXJlIHdhcyBub2lzZSBvbgp0aGUgZGlnaXRpemVy LiAgSSBjb3VsZCBiZSB3cm9uZywgYnV0IEkgZG9uJ3QgdGhpbmsgdGhlcmUncyBhbnkgd2F5CmN1 cnJlbnRseSB0byBiZSBhYmxlIHRvIHNwZWNpZnkgZXhhY3RseSB3aGF0IHRpbWluZ3Mgc2hvdWxk IGJlIHVzZWQgb24KYSBwYXJ0aWN1bGFyIGJvYXJkLgoKRG9uJ3QgZ2V0IGJlIHdyb25nLS1JIHRo aW5rIGEgcGF0Y2ggc3VjaCBhcyB0aGlzIG9uZSB0aGF0IGNsYWltcyBhCnNpbmdsZSBib2FyZCdz IHRpbWluZ3MgYXMgdGhlICJyaWdodCIgb25lcyBmb3IgYSBnZW5lcmljIHBhbmVsIGlzIGEKYml0 IG9mIGEgaGFjay4gIC4uLmJ1dCBhdCB0aGUgc2FtZSB0aW1lIHRoZXJlIGFyZSBubyBvdGhlciB1 c2VycyBvZgp0aGlzIHBhbmVsICh0aGF0IEkga25vdyBvZikgaW4gbWFpbmxpbmUgYW5kIHRoZSB0 aW1pbmdzIHByZXNlbnRlZCBoZXJlCmFyZSBjZXJ0YWlubHkgc2FuZSB0aW1pbmdzIGZvciB0aGlz IHBhbmVsLgoKSW4gYW55IGNhc2UsIHByZXZpb3VzIGRpc2N1c3Npb24gYXQ6IGh0dHBzOi8vcGF0 Y2h3b3JrLmtlcm5lbC5vcmcvcGF0Y2gvOTYxNDYwMy8KCgouLi5vaCwgYW5kIGxvb2tpbmcgYXQg dGhlIHByZXZpb3VzIGRpc2N1c3Npb24gcmVtaW5kcyBtZSB0aGF0IHRoZQp0aW1pbmdzIHByZXNl bnRlZCBpbiB0aGlzIGhlcmUgcGF0Y2ggYXJlIGFjdHVhbGx5IG5vdCB0aGUgcmlnaHQgb25lcwoo dGhleSBoYXZlIHRoZSByaWdodCBQTEwsIGJ1dCB0aGUgd3JvbmcgYmxhbmtpbmdzIHRvIGF2b2lk IHRoZSBub2lzZQppc3N1ZXMpLiAgU2VlIDwvL2Nocm9taXVtLXJldmlldy5nb29nbGVzb3VyY2Uu Y29tLzM4MTAxNT4KCgoKLURvdWcKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRl c2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8v ZHJpLWRldmVsCg==