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From: Doug Anderson <dianders@chromium.org>
To: Akash Asthana <akashast@codeaurora.org>
Cc: Stephen Boyd <swboyd@chromium.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Wolfram Sang <wsa@kernel.org>,
	linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	linux-i2c@vger.kernel.org, Andy Gross <agross@kernel.org>,
	Girish Mahadevan <girishm@codeaurora.org>,
	Karthikeyan Ramasubramanian <kramasub@codeaurora.org>,
	Mukesh Kumar Savaliya <msavaliy@codeaurora.org>,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/3] soc: qcom: geni: More properly switch to DMA mode
Date: Tue, 13 Oct 2020 14:35:42 -0700	[thread overview]
Message-ID: <CAD=FV=VWPqswOXJejyXjYT_Yspdu75ELq42cffN87FrpTwPUQg@mail.gmail.com> (raw)
In-Reply-To: <2ccc26a0-5d54-e06c-5a73-7eb353c393d2@codeaurora.org>

Hi,

On Mon, Oct 12, 2020 at 2:05 AM Akash Asthana <akashast@codeaurora.org> wrote:
>
> Hi Stephen,
>
>
> >>
> >>   static void geni_se_select_dma_mode(struct geni_se *se)
> >>   {
> >> +       u32 proto = geni_se_read_proto(se);
> >>          u32 val;
> >>
> >>          geni_se_irq_clear(se);
> >>
> >> +       val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
> >> +       if (proto != GENI_SE_UART) {
> > Not a problem with this patch but it would be great if there was a
> > comment here (and probably in geni_se_select_fifo_mode() too) indicating
> > why GENI_SE_UART is special. Is it because GENI_SE_UART doesn't use the
> > main sequencer? I think that is the reason, but I forgot and reading
> > this code doesn't tell me that.
> >
> > Splitting the driver in this way where the logic is in the geni wrapper
> > and in the engine driver leads to this confusion.
>
> GENI_SE_UART uses main sequencer for TX and secondary for RX transfers
> because it is asynchronous in nature.
>
> That's why  RX related bits (M_RX_FIFO_WATERMARK_EN |
> M_RX_FIFO_LAST_EN)  are not enable in main sequencer for UART.
>
> (M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN) bits are controlled from UART
> driver, it's gets enabled and disabled multiple times from start_tx
> ,stop_tx respectively.

For now I've "solved" this by adding some comments (in the 3rd patch)
basically summarizing what Akash said.  I didn't want to go further
than that for now because it felt more important to get the i2c bug
fixed sooner rather than later and re-organizing would be a big enough
change that it'd probably need a few spins.

Our bug trackers don't make it trivially easy to file a public bug
tracking this and assign it to Qualcomm, but I've filed a bug asking
folks at Qualcomm to help with re-organizing things after my patch
series lands.  This is internally tracked at Google as b:170766462
("Rejigger geni_se_select_fifo_mode() / geni_se_select_dma_mode() to
not manage interrupt enables").

-Doug

  reply	other threads:[~2020-10-14  9:22 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-08 22:52 [PATCH 0/3] i2c: i2c-qcom-geni: More properly fix the DMA race Douglas Anderson
2020-10-08 22:52 ` [PATCH 1/3] soc: qcom: geni: More properly switch to DMA mode Douglas Anderson
2020-10-10  0:39   ` Stephen Boyd
2020-10-12  9:05     ` Akash Asthana
2020-10-13 21:35       ` Doug Anderson [this message]
2020-10-12  8:09   ` Akash Asthana
2020-10-08 22:52 ` [PATCH 2/3] Revert "i2c: i2c-qcom-geni: Fix DMA transfer race" Douglas Anderson
2020-10-10  0:39   ` Stephen Boyd
2020-10-12  8:12   ` Akash Asthana
2020-10-08 22:52 ` [PATCH 3/3] soc: qcom: geni: Optimize select fifo/dma mode Douglas Anderson
2020-10-10  0:32   ` Stephen Boyd
2020-10-13 21:38     ` Doug Anderson
2020-10-10  0:26 ` [PATCH 0/3] i2c: i2c-qcom-geni: More properly fix the DMA race Stephen Boyd
2020-10-10 13:16 ` Dmitry Baryshkov

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