From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26AC5C4320A for ; Fri, 30 Jul 2021 22:20:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01CB2610E9 for ; Fri, 30 Jul 2021 22:20:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233072AbhG3WUz (ORCPT ); Fri, 30 Jul 2021 18:20:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233009AbhG3WUz (ORCPT ); Fri, 30 Jul 2021 18:20:55 -0400 Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E37AC0613C1 for ; Fri, 30 Jul 2021 15:20:49 -0700 (PDT) Received: by mail-qv1-xf30.google.com with SMTP id cg4so960635qvb.5 for ; Fri, 30 Jul 2021 15:20:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=X/ut0W8QWQzgc3+TFp0Zpab3f8ktnZebi671B/GRa1s=; b=MyagQMiCCsM3Rrn6I1WUv92/Bb4Hoxpt54pGqOpfWtDctdM1tQkL6ciLcbY6UdDKg+ CHPIMI68YD94tESmrEfcGANjj5Cl0XwRrXRcwNL9k1ZbXaHmbVZH7THGiL7zV/RxUQ1c g511pq+mPaWbOHjDMSUZoOWqY8Uja0Hq1ANig= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=X/ut0W8QWQzgc3+TFp0Zpab3f8ktnZebi671B/GRa1s=; b=tYbYKkH6yaiiyawAZyEctqZ4D22PMTAXjKWlGvG1SbelUif0K8/5B2QSWZv8e/4d/B 2IrY70P7acmjpnqDJ4I+KS7/AON3jeo5dGVfZ7rP5VftGX6ttH2c6XrN82nOtA2LYhRN 6IQKNPWL/ulsD6wDLc4ic+P/To5uacUv+e6nk+kVs36jXOkU+PwM7MI1VIa5tY6qX3qS Ec8l4+XrGgTZzm8zFrDgtUOQabqqjN0WGPwGhl5cN9I0dlUHAmPjoTCYfcXWTgrvmT9V CooYY5eyDK1+4d86k7lxFfKnZA/DacZ8XcpE9tDXbwRr6kua17MSspgUmyj/eHjHJPen Q0zQ== X-Gm-Message-State: AOAM530Kc/CSmE49z5Int+SQsNzmTZ0HLVT8j+5yia4XWav0u7VKYhUM 5VE+ZeUGcEU8t0TjvI4asJltqjMmI6KlIw== X-Google-Smtp-Source: ABdhPJz4HGsNYEcqjn0YPYkWG6X2QP1qUPuiTTuIDQJ/+BtikVkyevV//3Nk7/AfB7B47Smu4KrOqA== X-Received: by 2002:a0c:9a03:: with SMTP id p3mr5244612qvd.40.1627683648139; Fri, 30 Jul 2021 15:20:48 -0700 (PDT) Received: from mail-yb1-f171.google.com (mail-yb1-f171.google.com. [209.85.219.171]) by smtp.gmail.com with ESMTPSA id n188sm1649439qke.54.2021.07.30.15.20.46 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 30 Jul 2021 15:20:46 -0700 (PDT) Received: by mail-yb1-f171.google.com with SMTP id a201so1953913ybg.12 for ; Fri, 30 Jul 2021 15:20:46 -0700 (PDT) X-Received: by 2002:a25:2904:: with SMTP id p4mr6090679ybp.276.1627683645881; Fri, 30 Jul 2021 15:20:45 -0700 (PDT) MIME-Version: 1.0 References: <1620807083-5451-1-git-send-email-sibis@codeaurora.org> <1620807083-5451-3-git-send-email-sibis@codeaurora.org> In-Reply-To: <1620807083-5451-3-git-send-email-sibis@codeaurora.org> From: Doug Anderson Date: Fri, 30 Jul 2021 15:20:34 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add cpu OPP tables To: Sibi Sankar Cc: Bjorn Andersson , Matthias Kaehlcke , Viresh Kumar , Stephen Boyd , Andy Gross , Rob Herring , "Rafael J. Wysocki" , linux-arm-msm , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , Linux PM Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Wed, May 12, 2021 at 1:11 AM Sibi Sankar wrote: > > Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs. > > Reviewed-by: Douglas Anderson > Signed-off-by: Sibi Sankar > --- > > V3: > * Rename cpu opp table nodes [Matthias] > * Rename opp phandles [Doug] > > Depends on the following patch series: > L3 Provider Support: https://lore.kernel.org/lkml/1618556290-28303-1-git-send-email-okukatla@codeaurora.org/ > CPUfreq Support: https://lore.kernel.org/lkml/1618020280-5470-2-git-send-email-tdas@codeaurora.org/ > RPMH Provider Support: https://lore.kernel.org/lkml/1619517059-12109-1-git-send-email-okukatla@codeaurora.org/ > > It also depends on L3 and cpufreq dt nodes from the ^^ series to not have > overlapping memory regions. > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 215 +++++++++++++++++++++++++++++++++++ > 1 file changed, 215 insertions(+) I see patch #1 in mainline now. Does that mean it's time to land patch #2 in the Qualcomm tree now? ...or maybe it needs to be re-posted? -Doug