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[209.85.222.41]) by smtp.gmail.com with ESMTPSA id z4sm7544793vsl.27.2020.08.11.13.06.24 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Aug 2020 13:06:24 -0700 (PDT) Received: by mail-ua1-f41.google.com with SMTP id u15so3874022uau.10 for ; Tue, 11 Aug 2020 13:06:24 -0700 (PDT) X-Received: by 2002:ab0:623:: with SMTP id f32mr9988390uaf.121.1597176383647; Tue, 11 Aug 2020 13:06:23 -0700 (PDT) MIME-Version: 1.0 References: <1597058460-16211-1-git-send-email-mkshah@codeaurora.org> <1597058460-16211-3-git-send-email-mkshah@codeaurora.org> <159717444178.1360974.6520145243224264090@swboyd.mtv.corp.google.com> In-Reply-To: <159717444178.1360974.6520145243224264090@swboyd.mtv.corp.google.com> From: Doug Anderson Date: Tue, 11 Aug 2020 13:06:12 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 2/7] pinctrl: qcom: Use return value from irq_set_wake call To: Stephen Boyd Cc: Maulik Shah , Bjorn Andersson , Evan Green , LinusW , Marc Zyngier , Matthias Kaehlcke , LKML , linux-arm-msm , "open list:GPIO SUBSYSTEM" , Andy Gross , Thomas Gleixner , Jason Cooper , Rajendra Nayak , Lina Iyer , Srinivas Rao L Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Tue, Aug 11, 2020 at 12:34 PM Stephen Boyd wrote: > > Quoting Maulik Shah (2020-08-10 04:20:55) > > msmgpio irqchip is not using return value of irq_set_wake call. > > Start using it. > > Does this work when the irq parent isn't setup in a hierarchy? I seem to > recall that this was written this way because sometimes > irq_set_irq_wake() would fail for the summary irq so it was a best > effort setting of wake on the summary line. > > > > > Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") > > Signed-off-by: Maulik Shah > > Reviewed-by: Douglas Anderson > > --- > > drivers/pinctrl/qcom/pinctrl-msm.c | 8 +++----- > > 1 file changed, 3 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > > index 90edf61..c264561 100644 > > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > > @@ -1077,12 +1077,10 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) > > * when TLMM is powered on. To allow that, enable the GPIO > > * summary line to be wakeup capable at GIC. > > */ > > - if (d->parent_data) > > - irq_chip_set_wake_parent(d, on); > > - > > - irq_set_irq_wake(pctrl->irq, on); > > + if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) > > + return irq_chip_set_wake_parent(d, on); > > So this bit is probably fine. > > > > > - return 0; > > + return irq_set_irq_wake(pctrl->irq, on); > > But this one is probably not fine. Interesting. I wasn't aware of the history and thus assumed this was a bug. If Stephen is remembering correctly, please add a comment saying that we are purposely ignoring the return value in this case. -Doug