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[209.85.217.41]) by smtp.gmail.com with ESMTPSA id l11sm2868766vkm.20.2020.05.07.07.39.37 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 May 2020 07:39:38 -0700 (PDT) Received: by mail-vs1-f41.google.com with SMTP id l25so3507684vso.6 for ; Thu, 07 May 2020 07:39:37 -0700 (PDT) X-Received: by 2002:a67:f5d6:: with SMTP id t22mr12876499vso.73.1588862377337; Thu, 07 May 2020 07:39:37 -0700 (PDT) MIME-Version: 1.0 References: <20200430194617.197510-1-dianders@chromium.org> <20200430124442.v4.1.Ia50267a5549392af8b37e67092ca653a59c95886@changeid> In-Reply-To: <20200430124442.v4.1.Ia50267a5549392af8b37e67092ca653a59c95886@changeid> From: Doug Anderson Date: Thu, 7 May 2020 07:39:25 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 1/6] drm/bridge: ti-sn65dsi86: Export bridge GPIOs to Linux To: LinusW , Bartosz Golaszewski , David Airlie , Daniel Vetter , Rob Herring , Neil Armstrong , Andrzej Hajda , Laurent Pinchart , Sandeep Panda Cc: "open list:GPIO SUBSYSTEM" , Jonas Karlman , Rob Clark , Bjorn Andersson , Jeffrey Hugo , Jernej Skrabec , dri-devel , linux-arm-msm , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Stephen Boyd , LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Thu, Apr 30, 2020 at 12:46 PM Douglas Anderson wrote: > > The ti-sn65dsi86 MIPI DSI to eDP bridge chip has 4 pins on it that can > be used as GPIOs in a system. Each pin can be configured as input, > output, or a special function for the bridge chip. These are: > - GPIO1: SUSPEND Input > - GPIO2: DSIA VSYNC > - GPIO3: DSIA HSYNC or VSYNC > - GPIO4: PWM One suggestion that came off-list is to change the code to make the numbering match up better with the datasheet. Right now if you want GPIO 2 you have to refer to it like: hpd-gpios = <&sn65dsi86_bridge 1 GPIO_ACTIVE_HIGH>; That's because the code right now numbers things starting at 0 even if the datasheet numbers things starting at 1. I'm planning to spin the series later today for this. While at it, I'll squash my yaml bindings fixup into the bindings patch in this series. If someone would rather I wait and not spin yet, please yell. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98E84C54E4A for ; Thu, 7 May 2020 14:39:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 699A220575 for ; Thu, 7 May 2020 14:39:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="oKrgg6+o" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 699A220575 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 756656E122; Thu, 7 May 2020 14:39:41 +0000 (UTC) Received: from mail-vk1-xa44.google.com (mail-vk1-xa44.google.com [IPv6:2607:f8b0:4864:20::a44]) by gabe.freedesktop.org (Postfix) with ESMTPS id DFC5B6E122 for ; Thu, 7 May 2020 14:39:40 +0000 (UTC) Received: by mail-vk1-xa44.google.com with SMTP id i185so1536894vki.12 for ; Thu, 07 May 2020 07:39:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Z7IFA9stGr7AQIAUx30OK+wSMM9GgogchHTSn33YI0U=; b=oKrgg6+ohJKVAOjUfdVbli6fopWWBK9ouxsK7MkYl2D0qBOvCFhQahNLKGcyctP0/3 GuQCx6TcEKb7uN2XV751z4mfwU5kpykWAbuevm+p41uR8/egw097FPbwgDTfIlAaV1bB mk+N35TAXodLwzAsbM5yVi87spgJIxwJ/nNIM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Z7IFA9stGr7AQIAUx30OK+wSMM9GgogchHTSn33YI0U=; b=b6qaE8H6EVvZf7EoqHf0PJC2o6TPc4Co4g1TSFTM5bTxOVTPMNYOvfmwSxZ82+0AcP FcWypCZwoWitXTFFlRrlgOazUR4y9WciuAEyRHU4C+h2eyGL6E5awgy88y0OnFBRzbIs Qh1cfsU6rt08M5TI6XX/Sj0jK9xAaLfD8sYu5yLTEgKn8c+qV4flh7Prtsxm29k1TUqB hpRf1vJBUNNJalztLIFU2nmCwFYvTu4ulrivXD7kUwTYrkuVKIIf0PUqERUGSZpcp6fB JsGGB5BnOp0V+syBtsFBz0kVyOizQ4EdrVlfDLZ/XqkXbDTKx1EFH05NIUaxUhO9ybLr j11w== X-Gm-Message-State: AGi0PuYidRnrp10W53W1OzO10WEaLbF5HYbN3WhnuH+uySLEnQv7TXuC zg4GOg3FaT5ieE7084FSnnZK1WSyqpI= X-Google-Smtp-Source: APiQypK83K5XpjkZswfVXUrrcCDHBsO9vxjhDFMGcWh8WNQGPtclGPT6LfYQpFO6inLB7l7KUfAGZg== X-Received: by 2002:a1f:c1:: with SMTP id 184mr11796144vka.62.1588862379734; Thu, 07 May 2020 07:39:39 -0700 (PDT) Received: from mail-vs1-f51.google.com (mail-vs1-f51.google.com. [209.85.217.51]) by smtp.gmail.com with ESMTPSA id m203sm2950671vkm.54.2020.05.07.07.39.37 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 May 2020 07:39:38 -0700 (PDT) Received: by mail-vs1-f51.google.com with SMTP id 1so3487548vsl.9 for ; Thu, 07 May 2020 07:39:37 -0700 (PDT) X-Received: by 2002:a67:f5d6:: with SMTP id t22mr12876499vso.73.1588862377337; Thu, 07 May 2020 07:39:37 -0700 (PDT) MIME-Version: 1.0 References: <20200430194617.197510-1-dianders@chromium.org> <20200430124442.v4.1.Ia50267a5549392af8b37e67092ca653a59c95886@changeid> In-Reply-To: <20200430124442.v4.1.Ia50267a5549392af8b37e67092ca653a59c95886@changeid> From: Doug Anderson Date: Thu, 7 May 2020 07:39:25 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 1/6] drm/bridge: ti-sn65dsi86: Export bridge GPIOs to Linux To: LinusW , Bartosz Golaszewski , David Airlie , Daniel Vetter , Rob Herring , Neil Armstrong , Andrzej Hajda , Laurent Pinchart , Sandeep Panda X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Jernej Skrabec , Jeffrey Hugo , linux-arm-msm , Jonas Karlman , LKML , dri-devel , Bjorn Andersson , "open list:GPIO SUBSYSTEM" , Stephen Boyd Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, On Thu, Apr 30, 2020 at 12:46 PM Douglas Anderson wrote: > > The ti-sn65dsi86 MIPI DSI to eDP bridge chip has 4 pins on it that can > be used as GPIOs in a system. Each pin can be configured as input, > output, or a special function for the bridge chip. These are: > - GPIO1: SUSPEND Input > - GPIO2: DSIA VSYNC > - GPIO3: DSIA HSYNC or VSYNC > - GPIO4: PWM One suggestion that came off-list is to change the code to make the numbering match up better with the datasheet. Right now if you want GPIO 2 you have to refer to it like: hpd-gpios = <&sn65dsi86_bridge 1 GPIO_ACTIVE_HIGH>; That's because the code right now numbers things starting at 0 even if the datasheet numbers things starting at 1. I'm planning to spin the series later today for this. While at it, I'll squash my yaml bindings fixup into the bindings patch in this series. If someone would rather I wait and not spin yet, please yell. _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel