From: Doug Anderson <dianders@chromium.org>
To: Jisheng Zhang <jszhang@marvell.com>
Cc: Guenter Roeck <linux@roeck-us.net>,
Wim Van Sebroeck <wim@iguana.be>,
Heiko Stuebner <heiko@sntech.de>,
Lunxue Dai <lunxue.dai@rock-chips.com>,
Dinh Nguyen <dinguyen@altera.com>,
"linux-watchdog@vger.kernel.org" <linux-watchdog@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] watchdog: dw_wdt: pat the watchdog before enabling it
Date: Mon, 26 Jan 2015 09:01:37 -0800 [thread overview]
Message-ID: <CAD=FV=WKeH2hmgsB1Hh8G6LWGqSVf_nOTCs7PVqLZV_gB_VqhA@mail.gmail.com> (raw)
In-Reply-To: <20150126142210.4cd0b33f@xhacker>
Jisheng,
On Sun, Jan 25, 2015 at 10:22 PM, Jisheng Zhang <jszhang@marvell.com> wrote:
>> Specifically I see the register WDT_TORR that has an offset of 0x4.
>> That's the RANGE_REG in your code. It shows bits 3:0 set the timeout
>> period (0 = 0xffff and 15 = 0x7fffffff). It shows bits 31:4 as
>> "reserved".
>
> Could you please dump registers' value at offset 0xf4 and 0xf8 if you don't mind?
Those are not documented in the user manual that I have, but:
>>> r(0xff8000f4)
0x10000a02
>>> r(0xff8000f8)
0x3130332a
-Doug
next prev parent reply other threads:[~2015-01-26 17:01 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-21 23:17 [PATCH 1/2] watchdog: dw_wdt: pat the watchdog before enabling it Doug Anderson
2015-01-21 23:17 ` [PATCH 2/2] watchdog: dw_wdt: Try to get a 30 second watchdog by default Doug Anderson
2015-01-21 23:36 ` Guenter Roeck
2015-01-21 23:35 ` [PATCH 1/2] watchdog: dw_wdt: pat the watchdog before enabling it Guenter Roeck
2015-01-22 5:22 ` Jisheng Zhang
2015-01-22 5:31 ` Guenter Roeck
2015-01-22 17:09 ` Doug Anderson
2015-01-23 16:03 ` Guenter Roeck
2015-01-23 16:20 ` Doug Anderson
2015-01-23 17:02 ` Guenter Roeck
2015-01-26 6:22 ` Jisheng Zhang
2015-01-26 17:01 ` Doug Anderson [this message]
2015-01-27 3:44 ` Jisheng Zhang
2015-01-27 4:07 ` Guenter Roeck
2015-01-27 4:36 ` Jisheng Zhang
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