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[209.85.219.174]) by smtp.gmail.com with ESMTPSA id f15sm1386493qtv.60.2021.07.29.09.08.01 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Jul 2021 09:08:02 -0700 (PDT) Received: by mail-yb1-f174.google.com with SMTP id a201so10979336ybg.12 for ; Thu, 29 Jul 2021 09:08:01 -0700 (PDT) X-Received: by 2002:a25:b845:: with SMTP id b5mr7441639ybm.343.1627574881505; Thu, 29 Jul 2021 09:08:01 -0700 (PDT) MIME-Version: 1.0 References: <1627560036-1626-1-git-send-email-rnayak@codeaurora.org> <1627560036-1626-3-git-send-email-rnayak@codeaurora.org> In-Reply-To: <1627560036-1626-3-git-send-email-rnayak@codeaurora.org> From: Doug Anderson Date: Thu, 29 Jul 2021 09:07:50 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 2/3] nvmem: qfprom: sc7280: Handle the additional power-domains vote To: Rajendra Nayak Cc: Andy Gross , Bjorn Andersson , Srinivas Kandagatla , Rob Herring , linux-arm-msm , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , "Ravi Kumar Bokka (Temp)" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Thu, Jul 29, 2021 at 5:01 AM Rajendra Nayak wrote: > > On sc7280, to reliably blow fuses, we need an additional vote > on max performance state of 'MX' power-domain. > Add support for power-domain performance state voting in the > driver. > > Signed-off-by: Rajendra Nayak > --- > drivers/nvmem/qfprom.c | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c > index 81fbad5..b5f27df 100644 > --- a/drivers/nvmem/qfprom.c > +++ b/drivers/nvmem/qfprom.c > @@ -12,6 +12,8 @@ > #include > #include > #include > +#include > +#include > #include > #include > > @@ -139,6 +141,9 @@ static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv, > { > int ret; > > + dev_pm_genpd_set_performance_state(priv->dev, 0); > + pm_runtime_put(priv->dev); To me it feels as if this should be at the end of the function rather than the beginning. I guess it doesn't matter (?), but it feels wrong that we have writes to the register space after we're don't a pm_runtime_put(). > @@ -420,6 +440,12 @@ static int qfprom_probe(struct platform_device *pdev) > econfig.reg_write = qfprom_reg_write; > } > > + ret = devm_add_action_or_reset(dev, qfprom_runtime_disable, dev); > + if (ret) > + return ret; > + > + pm_runtime_enable(dev); > + Swap the order of the two. IOW first pm_runtime_enable(), then devm_add_action_or_reset(). Specifically the "_or_reset" means that if you fail to add the action (AKA devm_add_action() fails to allocate the tiny amount of memory it needs) it will actually _call_ the action. That means that in your code if the memory allocation fails you'll call pm_runtime_disable() without the corresponding pm_runtime_enable(). Other than those two issues this looks good to me. Feel free to add my Reviewed-by when you fix them. -Doug