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[209.85.217.45]) by smtp.gmail.com with ESMTPSA id c10sm27400vsq.1.2021.01.12.16.01.37 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Jan 2021 16:01:37 -0800 (PST) Received: by mail-vs1-f45.google.com with SMTP id o19so174432vsn.3 for ; Tue, 12 Jan 2021 16:01:37 -0800 (PST) X-Received: by 2002:a67:7385:: with SMTP id o127mr2228991vsc.8.1610496096878; Tue, 12 Jan 2021 16:01:36 -0800 (PST) MIME-Version: 1.0 References: <20210111151651.1616813-1-vkoul@kernel.org> In-Reply-To: <20210111151651.1616813-1-vkoul@kernel.org> From: Doug Anderson Date: Tue, 12 Jan 2021 16:01:24 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 0/7] Add and enable GPI DMA users To: Vinod Koul Cc: Bjorn Andersson , Mark Brown , Wolfram Sang , linux-arm-msm , Andy Gross , Matthias Kaehlcke , Sumit Semwal , Amit Pundir , linux-spi , linux-i2c@vger.kernel.org, LKML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Mon, Jan 11, 2021 at 7:17 AM Vinod Koul wrote: > > Hello, > > This series add the GPI DMA in qcom geni spi and i2c drivers. For this we > first need to move GENI_IF_DISABLE_RO and struct geni_wrapper to common > headers and then add support for gpi dma in geni driver. > > Then we add spi and i2c geni driver changes to support this DMA. > > Lastly, add the GPI dma nodes and enable dma for spi found in Rb3 board. > > To merge this, we could merge all thru qcom tree with ack on spi/i2c. It'd be super great if somewhere (ideally in the commit message and maybe somewhere in the code) you could talk more about the different modes. Maybe something like this (if it's correct): GPI Mode (confusingly, also known as "GSI" mode in some places): In this mode something else running on the SoC is sharing access to the geni instance. This mode allows sharing the device between the Linux kernel and other users including handling the fact that other users might be running the geni port at a different clock rate. GPI mode limits what you can do with a port. For instance, direct control of chip select is not allowed. NOTE: if firmware has configured a geni instance for GPI then FIFO and SE_DMA usage is not allowed. Conversely, if firmware has not configured a geni instance for GPI then only FIFO and SE_DMA usage is allowed. SE DMA Mode: Data transfers happen over DMA. SE FIFO Mode: Data is manually transferred into the FIFO by the CPU.