From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
	id S1753734AbcDVFdZ (ORCPT <rfc822;w@1wt.eu>);
	Fri, 22 Apr 2016 01:33:25 -0400
Received: from mail-wm0-f66.google.com ([74.125.82.66]:32815 "EHLO
	mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
	with ESMTP id S1751554AbcDVFdY (ORCPT
	<rfc822;linux-kernel@vger.kernel.org>);
	Fri, 22 Apr 2016 01:33:24 -0400
MIME-Version: 1.0
In-Reply-To: <20160307095021.7f9f7484@arm.com>
References: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com>
	<1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com>
	<20160307095021.7f9f7484@arm.com>
Date: Fri, 22 Apr 2016 00:33:22 -0500
Message-ID: <CADRPPNRU=qy34p4hzYvzBPrt2uabSQfc0Xdd8K5v5B_JW01QJA@mail.gmail.com>
Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support
From: Leo Li <pku.leo@gmail.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Minghuan Lian <Minghuan.Lian@nxp.com>,
        "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
        lkml <linux-kernel@vger.kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>, Roy Zang <roy.zang@nxp.com>,
        Mingkai Hu <mingkai.hu@nxp.com>, Stuart Yoder <stuart.yoder@nxp.com>,
        Yang-Leo Li <leoyang.li@nxp.com>, Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <Mark.Rutland@arm.com>
Content-Type: text/plain; charset=UTF-8
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On Mon, 7 Mar 2016 11:36:22 +0800
> Minghuan Lian <Minghuan.Lian@nxp.com> wrote:
>
>> Some kind of NXP Layerscape SoC provides a MSI
>> implementation which uses two SCFG registers MSIIR and
>> MSIR to support 32 MSI interrupts for each PCIe controller.
>> The patch is to support it.
>>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>
> The DT binding still needs an Ack from the DT maintainers though (cc'd).

Marc,

Who will be responsible to pick this driver?  I see you are also one
of the maintainers for irqchip.  Can you pick up the driver?  The
binding has already gotten ACKed by the device tree maintainer.

Regards,
Leo

From mboxrd@z Thu Jan  1 00:00:00 1970
From: pku.leo@gmail.com (Leo Li)
Date: Fri, 22 Apr 2016 00:33:22 -0500
Subject: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support
In-Reply-To: <20160307095021.7f9f7484@arm.com>
References: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com>
 <1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com>
 <20160307095021.7f9f7484@arm.com>
Message-ID: <CADRPPNRU=qy34p4hzYvzBPrt2uabSQfc0Xdd8K5v5B_JW01QJA@mail.gmail.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On Mon, 7 Mar 2016 11:36:22 +0800
> Minghuan Lian <Minghuan.Lian@nxp.com> wrote:
>
>> Some kind of NXP Layerscape SoC provides a MSI
>> implementation which uses two SCFG registers MSIIR and
>> MSIR to support 32 MSI interrupts for each PCIe controller.
>> The patch is to support it.
>>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>
> The DT binding still needs an Ack from the DT maintainers though (cc'd).

Marc,

Who will be responsible to pick this driver?  I see you are also one
of the maintainers for irqchip.  Can you pick up the driver?  The
binding has already gotten ACKed by the device tree maintainer.

Regards,
Leo