From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE75DC43331 for ; Mon, 11 Nov 2019 23:40:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 74DD7214DB for ; Mon, 11 Nov 2019 23:40:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727438AbfKKXkF (ORCPT ); Mon, 11 Nov 2019 18:40:05 -0500 Received: from mail-oi1-f196.google.com ([209.85.167.196]:35785 "EHLO mail-oi1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726923AbfKKXkE (ORCPT ); Mon, 11 Nov 2019 18:40:04 -0500 Received: by mail-oi1-f196.google.com with SMTP id n16so13138168oig.2 for ; Mon, 11 Nov 2019 15:40:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rYJ3hr5T5tZC4vSB8BbaPI2/bk6dIa1jNkM2nXBTPBI=; b=nFtBj/M8KtA8lR3cHWblAuQgt+FtDp+9rUVSz7E+UUMqNn5QKowIMB0xjZ8LXm1B/g eR4OsqMv27ZVmWI40oHtgntixm7dxXzqMRddS4ZwHVVQmszgtYO1uRU1ChYtRfKLjU1z 2knHOuQadur2EdCzEYoR1SMej1/nkTqXRdJYV29dd9MlDtXfmq3mUeeLUKZUs4RRyJ1+ gmzmd6MJHUAJBiBf50ogVZ4LHoS/nJVFLU3WXIESc1lAvCJi0KVSTaclGYkeiSkGwxKj A+WktAwbzoQN+5ZVPMDm7itA6GGE2SSC8i08t0tl0i06lKGyFgD6DznuxZRPV/DYZf2D OWIg== X-Gm-Message-State: APjAAAXjy95CUfE+hbRD3+bPFyBMz7kGZ3So8uwVcurUTscFTdjgnOnr Pymf5E6F1Wq+LZfH2V2tlpL4E+th X-Google-Smtp-Source: APXvYqxqEqNGm6TqPYNZNA2tXJ2n5Xd/iAqOlXrb51AN8akSpX1jBfackQQsV3W9dmeZ6b11Kd5uFQ== X-Received: by 2002:aca:417:: with SMTP id 23mr1376067oie.125.1573515603170; Mon, 11 Nov 2019 15:40:03 -0800 (PST) Received: from mail-oi1-f177.google.com (mail-oi1-f177.google.com. [209.85.167.177]) by smtp.gmail.com with ESMTPSA id h79sm5332530oib.3.2019.11.11.15.40.01 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Nov 2019 15:40:01 -0800 (PST) Received: by mail-oi1-f177.google.com with SMTP id v138so13104474oif.6 for ; Mon, 11 Nov 2019 15:40:01 -0800 (PST) X-Received: by 2002:aca:1205:: with SMTP id 5mr1320355ois.51.1573515600853; Mon, 11 Nov 2019 15:40:00 -0800 (PST) MIME-Version: 1.0 References: <20191108130123.6839-1-linux@rasmusvillemoes.dk> In-Reply-To: <20191108130123.6839-1-linux@rasmusvillemoes.dk> From: Li Yang Date: Mon, 11 Nov 2019 17:39:49 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 00/47] QUICC Engine support on ARM and ARM64 To: Rasmus Villemoes , David Miller , Scott Wood , Greg Kroah-Hartman , Timur Tabi , Qiang Zhao Cc: Christophe Leroy , linuxppc-dev , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , lkml Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 8, 2019 at 7:05 AM Rasmus Villemoes wrote: > I'm generally ok with these enhencements and cleanups. But as the whole patch series touched multiple subsystems, I would like to collect the Acked-by from Scott, Greg and David if we want the whole series to go through the fsl/soc tree. Also Qiang, can you help to test the latest version and provide you Tested-by? Thanks. > There have been several attempts in the past few years to allow > building the QUICC engine drivers for platforms other than PPC. This > is yet another attempt. > > v3 can be found here: https://lore.kernel.org/lkml/20191101124210.14510-1-linux@rasmusvillemoes.dk/ > > v4 adds a some patches to fix (ab)use of IS_ERR_VALUE which fails when > sizeof(u32) != sizeof(long), i.e. on 64-bit platforms. Freescale > drivers are some of the last holdouts using that macro (outside of > arch/ and core mm code), so I decided trying to simply get rid of it > instead of papering over it by using a temporary long to store the > result in. Doing that I stumbled on some other things that should be > fixed. These are the new patches 34-45. > > Patch 35 from v3 (which added a PPC32 dependency to FSL_UCC_HDLC) is > gone from this version, so that that driver can indeed now be built > for arm and arm64. > > 1-5 are about replacing in_be32 etc. in the core QE code (drivers/soc/fsl/qe). > > 6-8 handle miscellaneous other ppcisms. > > 9-21 deal with qe_ic: Simplifying the driver significantly by removing > unused code, and removing the platform-specific initialization from > arch/powerpc/. > > 22-25 deal with raw access to devicetree properties in native endianness. > > 26-33 makes drivers/tty/serial/ucc_uart.c (CONFIG_SERIAL_QE) ready to build on arm. > > 34-45 deal with IS_ERR_VALUE() and some other things found while > digging around that part of the code. > > 46 adds a PPC32 dependency to UCC_GETH - it has some of the same > issues that have been fixed in the ucc_uart and ucc_hdlc cases. Nobody > has requested that I allow that driver to be built for arm{,64}, so > instead of growing this series even bigger, I kept that addition. It's > trivial to remove if somebody cares enough to fix the build > errors/warnings and actually has a platform to test the result on. > > Finally patch 47 lifts the PPC32 restriction from QUICC_ENGINE. At the > request of Li Yang, it doesn't remove the PPC32 dependency but instead > changes it to PPC32 || ARM || ARM64 (or COMPILE_TEST), i.e. listing > the platforms that may have a QE. > > The series has been built and booted on both an mpc8309-based platform > (ppc) as well as an ls1021a-based platform (arm). The core QE code is > exercised on both, while I could only test the ucc_uart on arm, since > the uarts are not wired up on our mpc8309 board. Qiang Zhao reports > that the ucc_hdlc driver does indeed work on a ls1043ardb (arm64) > board, I hope he'll formally add a Tested-by: to the relevant patches > since I don't have any arm64 board with QE. > > Rasmus Villemoes (47): > soc: fsl: qe: remove space-before-tab > soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs > soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers > soc: fsl: qe: introduce qe_io{read,write}* wrappers > soc: fsl: qe: avoid ppc-specific io accessors > soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic > soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32 > soc: fsl: qe: drop unneeded #includes > soc: fsl: qe: drop assign-only high_active in qe_ic_init > soc: fsl: qe: remove pointless sysfs registration in qe_ic.c > soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx > soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/ > powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ > powerpc/85xx: remove mostly pointless mpc85xx_qe_init() Scott, What do you think about the PPC changes? > soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c > soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low > soc: fsl: qe: remove unused qe_ic_set_* functions > soc: fsl: qe: don't use NO_IRQ in qe_ic.c > soc: fsl: qe: make qe_ic_get_{low,high}_irq static > soc: fsl: qe: simplify qe_ic_init() > soc: fsl: qe: merge qe_ic.h headers into qe_ic.c > soc: fsl: qe: qe.c: use of_property_read_* helpers > soc: fsl: qe: qe_io.c: don't open-code of_parse_phandle() > soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu > soc: fsl: qe: qe_io.c: use of_property_read_u32() in par_io_init() > soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl > soc/fsl/qe/qe.h: update include path for cpm.h > serial: ucc_uart: explicitly include soc/fsl/cpm.h > serial: ucc_uart: replace ppc-specific IO accessors > serial: ucc_uart: factor out soft_uart initialization > serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32 > serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe() > serial: ucc_uart: access __be32 field using be32_to_cpu Greg and Timur, What do you think about these serial changes. > soc: fsl: qe: change return type of cpm_muram_alloc() to s32 > soc: fsl: qe: make cpm_muram_free() return void > soc: fsl: qe: make cpm_muram_free() ignore a negative offset > soc: fsl: qe: drop broken lazy call of cpm_muram_init() > soc: fsl: qe: refactor cpm_muram_alloc_common to prevent BUG on error > path > soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c > soc: fsl: qe: drop use of IS_ERR_VALUE in qe_sdma_init() > soc: fsl: qe: drop pointless check in qe_sdma_init() > soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c > net/wan/fsl_ucc_hdlc: avoid use of IS_ERR_VALUE() > net/wan/fsl_ucc_hdlc: fix reading of __be16 registers > net/wan/fsl_ucc_hdlc: reject muram offsets above 64K > net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32 David and Qiang, What do you think of the net changes? > soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE > > arch/powerpc/include/asm/cpm.h | 172 +------- > arch/powerpc/platforms/83xx/km83xx.c | 3 +- > arch/powerpc/platforms/83xx/misc.c | 23 -- > arch/powerpc/platforms/83xx/mpc832x_mds.c | 3 +- > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 3 +- > arch/powerpc/platforms/83xx/mpc836x_mds.c | 3 +- > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 3 +- > arch/powerpc/platforms/83xx/mpc83xx.h | 7 - > arch/powerpc/platforms/85xx/common.c | 23 -- > arch/powerpc/platforms/85xx/corenet_generic.c | 12 - > arch/powerpc/platforms/85xx/mpc85xx.h | 2 - > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 28 -- > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 18 - > arch/powerpc/platforms/85xx/twr_p102x.c | 16 - > drivers/net/ethernet/freescale/Kconfig | 2 +- > drivers/net/wan/fsl_ucc_hdlc.c | 23 +- > drivers/net/wan/fsl_ucc_hdlc.h | 2 +- > drivers/soc/fsl/qe/Kconfig | 3 +- > drivers/soc/fsl/qe/gpio.c | 34 +- > drivers/soc/fsl/qe/qe.c | 104 ++--- > drivers/soc/fsl/qe/qe_common.c | 50 +-- > drivers/soc/fsl/qe/qe_ic.c | 285 ++++++------- > drivers/soc/fsl/qe/qe_ic.h | 99 ----- > drivers/soc/fsl/qe/qe_io.c | 70 ++-- > drivers/soc/fsl/qe/qe_tdm.c | 8 +- > drivers/soc/fsl/qe/ucc.c | 26 +- > drivers/soc/fsl/qe/ucc_fast.c | 86 ++-- > drivers/soc/fsl/qe/ucc_slow.c | 60 ++- > drivers/soc/fsl/qe/usb.c | 2 +- > drivers/tty/serial/ucc_uart.c | 383 +++++++++--------- > include/soc/fsl/cpm.h | 171 ++++++++ > include/soc/fsl/qe/qe.h | 59 ++- > include/soc/fsl/qe/qe_ic.h | 135 ------ > include/soc/fsl/qe/ucc_fast.h | 4 +- > include/soc/fsl/qe/ucc_slow.h | 6 +- > 35 files changed, 770 insertions(+), 1158 deletions(-) > delete mode 100644 drivers/soc/fsl/qe/qe_ic.h > create mode 100644 include/soc/fsl/cpm.h > delete mode 100644 include/soc/fsl/qe/qe_ic.h > > -- > 2.23.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF11EC43331 for ; Mon, 11 Nov 2019 23:42:35 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0201A214DB for ; Mon, 11 Nov 2019 23:42:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0201A214DB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47BnVH6MFTzF4MF for ; Tue, 12 Nov 2019 10:42:31 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=209.85.167.196; helo=mail-oi1-f196.google.com; envelope-from=pku.leo@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from mail-oi1-f196.google.com (mail-oi1-f196.google.com [209.85.167.196]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47BnRT2QZ3zF4C7 for ; Tue, 12 Nov 2019 10:40:04 +1100 (AEDT) Received: by mail-oi1-f196.google.com with SMTP id e9so13118426oif.8 for ; Mon, 11 Nov 2019 15:40:04 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rYJ3hr5T5tZC4vSB8BbaPI2/bk6dIa1jNkM2nXBTPBI=; b=Vc3Sf5hGMdsgU1GAIcm86z6x5s/jWMGuB53P8w/VANQEfyI4nDCpBBOKs3fALaOeex OhwdTop6b5e0Z9doRr0+kLCdjKGgGzhpty5QDW24BBGJNxzV+Grp/sMlifZukyyNQq5m Ucsz/gP10kn3Mu7rGALbKMOnNLdMC4RMZu224rgSziXdwQTGNvSmVG84r+ncCb4PwcS4 MEGxEWKQvJMePrHtXtgnHgx/Xrib+Msbw+uyJahA4li5HC0rARwLpZRfq2qyKN5ERXAC aUA+JDr3WtlwYzzYuvgP0sj9kWJE7ruKG1OIv+zD/4ZdZT5vMRm4EfXU6BaNWEMaOu7e gttA== X-Gm-Message-State: APjAAAVXvRhnzumGTMLsy8ZtVtVkp0CxwO0jofdnKwOsqtCgqQp9up06 iDN9660cT6wRCJvVQRIkRaGW3bCQ X-Google-Smtp-Source: APXvYqyo2F10B/gLcw7T7ORtYHo74MROU+IzZG6rAxHMl0RFMsXfUfgwt/o0jQ9OWpCN1onIAS08tA== X-Received: by 2002:aca:5585:: with SMTP id j127mr1366646oib.133.1573515602239; Mon, 11 Nov 2019 15:40:02 -0800 (PST) Received: from mail-oi1-f173.google.com (mail-oi1-f173.google.com. [209.85.167.173]) by smtp.gmail.com with ESMTPSA id i195sm5547812oib.55.2019.11.11.15.40.01 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Nov 2019 15:40:01 -0800 (PST) Received: by mail-oi1-f173.google.com with SMTP id n16so13138090oig.2 for ; Mon, 11 Nov 2019 15:40:01 -0800 (PST) X-Received: by 2002:aca:1205:: with SMTP id 5mr1320355ois.51.1573515600853; Mon, 11 Nov 2019 15:40:00 -0800 (PST) MIME-Version: 1.0 References: <20191108130123.6839-1-linux@rasmusvillemoes.dk> In-Reply-To: <20191108130123.6839-1-linux@rasmusvillemoes.dk> From: Li Yang Date: Mon, 11 Nov 2019 17:39:49 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 00/47] QUICC Engine support on ARM and ARM64 To: Rasmus Villemoes , David Miller , Scott Wood , Greg Kroah-Hartman , Timur Tabi , Qiang Zhao Content-Type: text/plain; charset="UTF-8" X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev , lkml , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, Nov 8, 2019 at 7:05 AM Rasmus Villemoes wrote: > I'm generally ok with these enhencements and cleanups. But as the whole patch series touched multiple subsystems, I would like to collect the Acked-by from Scott, Greg and David if we want the whole series to go through the fsl/soc tree. Also Qiang, can you help to test the latest version and provide you Tested-by? Thanks. > There have been several attempts in the past few years to allow > building the QUICC engine drivers for platforms other than PPC. This > is yet another attempt. > > v3 can be found here: https://lore.kernel.org/lkml/20191101124210.14510-1-linux@rasmusvillemoes.dk/ > > v4 adds a some patches to fix (ab)use of IS_ERR_VALUE which fails when > sizeof(u32) != sizeof(long), i.e. on 64-bit platforms. Freescale > drivers are some of the last holdouts using that macro (outside of > arch/ and core mm code), so I decided trying to simply get rid of it > instead of papering over it by using a temporary long to store the > result in. Doing that I stumbled on some other things that should be > fixed. These are the new patches 34-45. > > Patch 35 from v3 (which added a PPC32 dependency to FSL_UCC_HDLC) is > gone from this version, so that that driver can indeed now be built > for arm and arm64. > > 1-5 are about replacing in_be32 etc. in the core QE code (drivers/soc/fsl/qe). > > 6-8 handle miscellaneous other ppcisms. > > 9-21 deal with qe_ic: Simplifying the driver significantly by removing > unused code, and removing the platform-specific initialization from > arch/powerpc/. > > 22-25 deal with raw access to devicetree properties in native endianness. > > 26-33 makes drivers/tty/serial/ucc_uart.c (CONFIG_SERIAL_QE) ready to build on arm. > > 34-45 deal with IS_ERR_VALUE() and some other things found while > digging around that part of the code. > > 46 adds a PPC32 dependency to UCC_GETH - it has some of the same > issues that have been fixed in the ucc_uart and ucc_hdlc cases. Nobody > has requested that I allow that driver to be built for arm{,64}, so > instead of growing this series even bigger, I kept that addition. It's > trivial to remove if somebody cares enough to fix the build > errors/warnings and actually has a platform to test the result on. > > Finally patch 47 lifts the PPC32 restriction from QUICC_ENGINE. At the > request of Li Yang, it doesn't remove the PPC32 dependency but instead > changes it to PPC32 || ARM || ARM64 (or COMPILE_TEST), i.e. listing > the platforms that may have a QE. > > The series has been built and booted on both an mpc8309-based platform > (ppc) as well as an ls1021a-based platform (arm). The core QE code is > exercised on both, while I could only test the ucc_uart on arm, since > the uarts are not wired up on our mpc8309 board. Qiang Zhao reports > that the ucc_hdlc driver does indeed work on a ls1043ardb (arm64) > board, I hope he'll formally add a Tested-by: to the relevant patches > since I don't have any arm64 board with QE. > > Rasmus Villemoes (47): > soc: fsl: qe: remove space-before-tab > soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs > soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers > soc: fsl: qe: introduce qe_io{read,write}* wrappers > soc: fsl: qe: avoid ppc-specific io accessors > soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic > soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32 > soc: fsl: qe: drop unneeded #includes > soc: fsl: qe: drop assign-only high_active in qe_ic_init > soc: fsl: qe: remove pointless sysfs registration in qe_ic.c > soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx > soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/ > powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ > powerpc/85xx: remove mostly pointless mpc85xx_qe_init() Scott, What do you think about the PPC changes? > soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c > soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low > soc: fsl: qe: remove unused qe_ic_set_* functions > soc: fsl: qe: don't use NO_IRQ in qe_ic.c > soc: fsl: qe: make qe_ic_get_{low,high}_irq static > soc: fsl: qe: simplify qe_ic_init() > soc: fsl: qe: merge qe_ic.h headers into qe_ic.c > soc: fsl: qe: qe.c: use of_property_read_* helpers > soc: fsl: qe: qe_io.c: don't open-code of_parse_phandle() > soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu > soc: fsl: qe: qe_io.c: use of_property_read_u32() in par_io_init() > soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl > soc/fsl/qe/qe.h: update include path for cpm.h > serial: ucc_uart: explicitly include soc/fsl/cpm.h > serial: ucc_uart: replace ppc-specific IO accessors > serial: ucc_uart: factor out soft_uart initialization > serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32 > serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe() > serial: ucc_uart: access __be32 field using be32_to_cpu Greg and Timur, What do you think about these serial changes. > soc: fsl: qe: change return type of cpm_muram_alloc() to s32 > soc: fsl: qe: make cpm_muram_free() return void > soc: fsl: qe: make cpm_muram_free() ignore a negative offset > soc: fsl: qe: drop broken lazy call of cpm_muram_init() > soc: fsl: qe: refactor cpm_muram_alloc_common to prevent BUG on error > path > soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c > soc: fsl: qe: drop use of IS_ERR_VALUE in qe_sdma_init() > soc: fsl: qe: drop pointless check in qe_sdma_init() > soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c > net/wan/fsl_ucc_hdlc: avoid use of IS_ERR_VALUE() > net/wan/fsl_ucc_hdlc: fix reading of __be16 registers > net/wan/fsl_ucc_hdlc: reject muram offsets above 64K > net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32 David and Qiang, What do you think of the net changes? > soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE > > arch/powerpc/include/asm/cpm.h | 172 +------- > arch/powerpc/platforms/83xx/km83xx.c | 3 +- > arch/powerpc/platforms/83xx/misc.c | 23 -- > arch/powerpc/platforms/83xx/mpc832x_mds.c | 3 +- > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 3 +- > arch/powerpc/platforms/83xx/mpc836x_mds.c | 3 +- > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 3 +- > arch/powerpc/platforms/83xx/mpc83xx.h | 7 - > arch/powerpc/platforms/85xx/common.c | 23 -- > arch/powerpc/platforms/85xx/corenet_generic.c | 12 - > arch/powerpc/platforms/85xx/mpc85xx.h | 2 - > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 28 -- > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 18 - > arch/powerpc/platforms/85xx/twr_p102x.c | 16 - > drivers/net/ethernet/freescale/Kconfig | 2 +- > drivers/net/wan/fsl_ucc_hdlc.c | 23 +- > drivers/net/wan/fsl_ucc_hdlc.h | 2 +- > drivers/soc/fsl/qe/Kconfig | 3 +- > drivers/soc/fsl/qe/gpio.c | 34 +- > drivers/soc/fsl/qe/qe.c | 104 ++--- > drivers/soc/fsl/qe/qe_common.c | 50 +-- > drivers/soc/fsl/qe/qe_ic.c | 285 ++++++------- > drivers/soc/fsl/qe/qe_ic.h | 99 ----- > drivers/soc/fsl/qe/qe_io.c | 70 ++-- > drivers/soc/fsl/qe/qe_tdm.c | 8 +- > drivers/soc/fsl/qe/ucc.c | 26 +- > drivers/soc/fsl/qe/ucc_fast.c | 86 ++-- > drivers/soc/fsl/qe/ucc_slow.c | 60 ++- > drivers/soc/fsl/qe/usb.c | 2 +- > drivers/tty/serial/ucc_uart.c | 383 +++++++++--------- > include/soc/fsl/cpm.h | 171 ++++++++ > include/soc/fsl/qe/qe.h | 59 ++- > include/soc/fsl/qe/qe_ic.h | 135 ------ > include/soc/fsl/qe/ucc_fast.h | 4 +- > include/soc/fsl/qe/ucc_slow.h | 6 +- > 35 files changed, 770 insertions(+), 1158 deletions(-) > delete mode 100644 drivers/soc/fsl/qe/qe_ic.h > create mode 100644 include/soc/fsl/cpm.h > delete mode 100644 include/soc/fsl/qe/qe_ic.h > > -- > 2.23.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3500C43331 for ; Mon, 11 Nov 2019 23:40:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BF362214DB for ; Mon, 11 Nov 2019 23:40:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="EN2/B111" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BF362214DB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2GQnB4Hu2Gz0NS+tJoZxGCqTJBubUfTQ03scQbriP44=; b=EN2/B111aBjv6M rofiogm1Ku/QP14mU4ZvMrPMI+ZDJh1TW8R8jd5Hfl9XU2apbAM1Or7/9Axv5uNe260Ye/Dapzc3A zOlaoQuSgOz0VXso94xzobynkA+k1IMrAWY9SXMxRYdbMqYu9AeXv9sApAFccgcF0DRAxQfjwuaHA +AO+eIZvph1BcxFhsp+4TKO8O50UOY7mKRF2QhzFVlvvbPZ2lIyM5GE5W8Jgf+xWKsCgLIlKOY6uu AF9F/AsGr33FX0V4yJMuwC3HNucjjBkRhb5TRcPS3kdurKsLvi6w3M9/9wV1Nlfm6yxmwg2dr/xXD r0N2TRie4+KO5MbJja9g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iUJI0-0000uv-Ci; Mon, 11 Nov 2019 23:40:08 +0000 Received: from mail-oi1-f195.google.com ([209.85.167.195]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iUJHw-0008Vr-2M for linux-arm-kernel@lists.infradead.org; Mon, 11 Nov 2019 23:40:06 +0000 Received: by mail-oi1-f195.google.com with SMTP id l20so13100746oie.10 for ; Mon, 11 Nov 2019 15:40:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rYJ3hr5T5tZC4vSB8BbaPI2/bk6dIa1jNkM2nXBTPBI=; b=tiDpZOjzJ6e7eCDh9pVqqwQ1qtaSsawTErcljS/knxPpCR8R5u1b+YeV82irfNc242 lOtgMjm6ceuaqDTnDjeWxWOLZi6jUI4L5FEhfYiaGfIprmC3s4SgzxlLlHPCrnT6VQsS YFXSju/cXownqLTNFRR/aVGzMWZH0Rsa4MPSTuA9CrUBdHGY4ZVmKw5soFNgrGk+hHHN BPNDEz5mCMs+AO3OZK3bAXP6AtkBgQ6OuooCPXEROXL01Qox3yaM2cZucpM9rMTglzRr 9BE4XLnpCS13qtGXXqwVEVXrb488gvugdmkBj6YKgn9uZ7KWOzPbymvU5JfAGRzOhzql vcAA== X-Gm-Message-State: APjAAAWc+OkGN+XOzmHwonLshyHueCKFRII6sku5FJXmMaZGxsqHEgei 8miEOH457brnFjTyF0bVHCuMkUp+ X-Google-Smtp-Source: APXvYqzo4JoYC9vDcAmfE2jptXf2+CgCWEDo1k+BW52TS60GY7HG3E7vQmprIo5Oi5lAABa1VgjRgw== X-Received: by 2002:aca:6c1:: with SMTP id 184mr1339118oig.84.1573515601590; Mon, 11 Nov 2019 15:40:01 -0800 (PST) Received: from mail-oi1-f169.google.com (mail-oi1-f169.google.com. [209.85.167.169]) by smtp.gmail.com with ESMTPSA id e19sm5270642otj.51.2019.11.11.15.40.01 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Nov 2019 15:40:01 -0800 (PST) Received: by mail-oi1-f169.google.com with SMTP id l202so13134910oig.1 for ; Mon, 11 Nov 2019 15:40:01 -0800 (PST) X-Received: by 2002:aca:1205:: with SMTP id 5mr1320355ois.51.1573515600853; Mon, 11 Nov 2019 15:40:00 -0800 (PST) MIME-Version: 1.0 References: <20191108130123.6839-1-linux@rasmusvillemoes.dk> In-Reply-To: <20191108130123.6839-1-linux@rasmusvillemoes.dk> From: Li Yang Date: Mon, 11 Nov 2019 17:39:49 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 00/47] QUICC Engine support on ARM and ARM64 To: Rasmus Villemoes , David Miller , Scott Wood , Greg Kroah-Hartman , Timur Tabi , Qiang Zhao X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191111_154004_116236_8683410E X-CRM114-Status: GOOD ( 30.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christophe Leroy , linuxppc-dev , lkml , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 8, 2019 at 7:05 AM Rasmus Villemoes wrote: > I'm generally ok with these enhencements and cleanups. But as the whole patch series touched multiple subsystems, I would like to collect the Acked-by from Scott, Greg and David if we want the whole series to go through the fsl/soc tree. Also Qiang, can you help to test the latest version and provide you Tested-by? Thanks. > There have been several attempts in the past few years to allow > building the QUICC engine drivers for platforms other than PPC. This > is yet another attempt. > > v3 can be found here: https://lore.kernel.org/lkml/20191101124210.14510-1-linux@rasmusvillemoes.dk/ > > v4 adds a some patches to fix (ab)use of IS_ERR_VALUE which fails when > sizeof(u32) != sizeof(long), i.e. on 64-bit platforms. Freescale > drivers are some of the last holdouts using that macro (outside of > arch/ and core mm code), so I decided trying to simply get rid of it > instead of papering over it by using a temporary long to store the > result in. Doing that I stumbled on some other things that should be > fixed. These are the new patches 34-45. > > Patch 35 from v3 (which added a PPC32 dependency to FSL_UCC_HDLC) is > gone from this version, so that that driver can indeed now be built > for arm and arm64. > > 1-5 are about replacing in_be32 etc. in the core QE code (drivers/soc/fsl/qe). > > 6-8 handle miscellaneous other ppcisms. > > 9-21 deal with qe_ic: Simplifying the driver significantly by removing > unused code, and removing the platform-specific initialization from > arch/powerpc/. > > 22-25 deal with raw access to devicetree properties in native endianness. > > 26-33 makes drivers/tty/serial/ucc_uart.c (CONFIG_SERIAL_QE) ready to build on arm. > > 34-45 deal with IS_ERR_VALUE() and some other things found while > digging around that part of the code. > > 46 adds a PPC32 dependency to UCC_GETH - it has some of the same > issues that have been fixed in the ucc_uart and ucc_hdlc cases. Nobody > has requested that I allow that driver to be built for arm{,64}, so > instead of growing this series even bigger, I kept that addition. It's > trivial to remove if somebody cares enough to fix the build > errors/warnings and actually has a platform to test the result on. > > Finally patch 47 lifts the PPC32 restriction from QUICC_ENGINE. At the > request of Li Yang, it doesn't remove the PPC32 dependency but instead > changes it to PPC32 || ARM || ARM64 (or COMPILE_TEST), i.e. listing > the platforms that may have a QE. > > The series has been built and booted on both an mpc8309-based platform > (ppc) as well as an ls1021a-based platform (arm). The core QE code is > exercised on both, while I could only test the ucc_uart on arm, since > the uarts are not wired up on our mpc8309 board. Qiang Zhao reports > that the ucc_hdlc driver does indeed work on a ls1043ardb (arm64) > board, I hope he'll formally add a Tested-by: to the relevant patches > since I don't have any arm64 board with QE. > > Rasmus Villemoes (47): > soc: fsl: qe: remove space-before-tab > soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs > soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers > soc: fsl: qe: introduce qe_io{read,write}* wrappers > soc: fsl: qe: avoid ppc-specific io accessors > soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic > soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32 > soc: fsl: qe: drop unneeded #includes > soc: fsl: qe: drop assign-only high_active in qe_ic_init > soc: fsl: qe: remove pointless sysfs registration in qe_ic.c > soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx > soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/ > powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ > powerpc/85xx: remove mostly pointless mpc85xx_qe_init() Scott, What do you think about the PPC changes? > soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c > soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low > soc: fsl: qe: remove unused qe_ic_set_* functions > soc: fsl: qe: don't use NO_IRQ in qe_ic.c > soc: fsl: qe: make qe_ic_get_{low,high}_irq static > soc: fsl: qe: simplify qe_ic_init() > soc: fsl: qe: merge qe_ic.h headers into qe_ic.c > soc: fsl: qe: qe.c: use of_property_read_* helpers > soc: fsl: qe: qe_io.c: don't open-code of_parse_phandle() > soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu > soc: fsl: qe: qe_io.c: use of_property_read_u32() in par_io_init() > soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl > soc/fsl/qe/qe.h: update include path for cpm.h > serial: ucc_uart: explicitly include soc/fsl/cpm.h > serial: ucc_uart: replace ppc-specific IO accessors > serial: ucc_uart: factor out soft_uart initialization > serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32 > serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe() > serial: ucc_uart: access __be32 field using be32_to_cpu Greg and Timur, What do you think about these serial changes. > soc: fsl: qe: change return type of cpm_muram_alloc() to s32 > soc: fsl: qe: make cpm_muram_free() return void > soc: fsl: qe: make cpm_muram_free() ignore a negative offset > soc: fsl: qe: drop broken lazy call of cpm_muram_init() > soc: fsl: qe: refactor cpm_muram_alloc_common to prevent BUG on error > path > soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c > soc: fsl: qe: drop use of IS_ERR_VALUE in qe_sdma_init() > soc: fsl: qe: drop pointless check in qe_sdma_init() > soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c > net/wan/fsl_ucc_hdlc: avoid use of IS_ERR_VALUE() > net/wan/fsl_ucc_hdlc: fix reading of __be16 registers > net/wan/fsl_ucc_hdlc: reject muram offsets above 64K > net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32 David and Qiang, What do you think of the net changes? > soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE > > arch/powerpc/include/asm/cpm.h | 172 +------- > arch/powerpc/platforms/83xx/km83xx.c | 3 +- > arch/powerpc/platforms/83xx/misc.c | 23 -- > arch/powerpc/platforms/83xx/mpc832x_mds.c | 3 +- > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 3 +- > arch/powerpc/platforms/83xx/mpc836x_mds.c | 3 +- > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 3 +- > arch/powerpc/platforms/83xx/mpc83xx.h | 7 - > arch/powerpc/platforms/85xx/common.c | 23 -- > arch/powerpc/platforms/85xx/corenet_generic.c | 12 - > arch/powerpc/platforms/85xx/mpc85xx.h | 2 - > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 28 -- > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 18 - > arch/powerpc/platforms/85xx/twr_p102x.c | 16 - > drivers/net/ethernet/freescale/Kconfig | 2 +- > drivers/net/wan/fsl_ucc_hdlc.c | 23 +- > drivers/net/wan/fsl_ucc_hdlc.h | 2 +- > drivers/soc/fsl/qe/Kconfig | 3 +- > drivers/soc/fsl/qe/gpio.c | 34 +- > drivers/soc/fsl/qe/qe.c | 104 ++--- > drivers/soc/fsl/qe/qe_common.c | 50 +-- > drivers/soc/fsl/qe/qe_ic.c | 285 ++++++------- > drivers/soc/fsl/qe/qe_ic.h | 99 ----- > drivers/soc/fsl/qe/qe_io.c | 70 ++-- > drivers/soc/fsl/qe/qe_tdm.c | 8 +- > drivers/soc/fsl/qe/ucc.c | 26 +- > drivers/soc/fsl/qe/ucc_fast.c | 86 ++-- > drivers/soc/fsl/qe/ucc_slow.c | 60 ++- > drivers/soc/fsl/qe/usb.c | 2 +- > drivers/tty/serial/ucc_uart.c | 383 +++++++++--------- > include/soc/fsl/cpm.h | 171 ++++++++ > include/soc/fsl/qe/qe.h | 59 ++- > include/soc/fsl/qe/qe_ic.h | 135 ------ > include/soc/fsl/qe/ucc_fast.h | 4 +- > include/soc/fsl/qe/ucc_slow.h | 6 +- > 35 files changed, 770 insertions(+), 1158 deletions(-) > delete mode 100644 drivers/soc/fsl/qe/qe_ic.h > create mode 100644 include/soc/fsl/cpm.h > delete mode 100644 include/soc/fsl/qe/qe_ic.h > > -- > 2.23.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel