From: Yaroslav Isakov <yaroslav.isakov@gmail.com>
To: Keith Busch <kbusch@kernel.org>
Cc: linux-nvme@lists.infradead.org
Subject: Re: NVME is not using CPU0
Date: Tue, 10 Mar 2020 00:29:38 +0100 [thread overview]
Message-ID: <CADS+iDVTaAViuKRvcSxyL3TngMWMjpvALEWhd1+Sfi_X3nZomA@mail.gmail.com> (raw)
In-Reply-To: <20200309141629.GA5446@redsun51.ssa.fujisawa.hgst.com>
Keith, thank you!
After some debugging, I've found that kernel is setting 8 queues in
NVME disk (which is, BTW, Samsung 960 Pro), and trying to create 9 IRQ
vectors, but it looks like device supports no more than 8:
> lspci -s 02:00.0 -v | grep MSI-X
> Capabilities: [b0] MSI-X: Enable+ Count=8 Masked-
So, I wonder, if this Count is hardware limit of device, and cannot be
raised (so, cannot be changed via SET_FEATURE 7)?
пн, 9 мар. 2020 г. в 15:16, Keith Busch <kbusch@kernel.org>:
>
> On Mon, Mar 09, 2020 at 10:49:43AM +0100, Yaroslav Isakov wrote:
> > Hello, Keith! I've tried to pin fio process's threads, but with no
> > luck. On my system, your command gave this:
> > 0, 1
> > 2
> > 3
> > 4
> > 5
> > 6
> > 7
> > So, it looks like first queue should use two CPUs, but using only
> > CPU1. Oh, and if I'm run fio with 2 threads, without pinning, I can
> > see increasing numbers in /proc/interrupts for all CPUs besides CPU0
>
> /proc/interrupts shows which cpu handled a completion. It doesn't show
> which CPU handled the submission. You don't have enough interrupt vectors
> to assign to each CPU so some CPUs won't get interrupts.
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next prev parent reply other threads:[~2020-03-09 23:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-08 23:46 NVME is not using CPU0 Yaroslav Isakov
2020-03-09 1:55 ` Keith Busch
2020-03-09 9:49 ` Yaroslav Isakov
2020-03-09 14:16 ` Keith Busch
2020-03-09 23:29 ` Yaroslav Isakov [this message]
2020-03-10 3:11 ` Keith Busch
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