From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dinh Nguyen Date: Wed, 6 Apr 2016 11:35:45 -0500 Subject: [U-Boot] SoCFPGA cache / S-bit problem - was Re: Newbie SPL question for socfpga_sockit In-Reply-To: <56F2B852.3090507@denx.de> References: <56C53059.4020505@electromag.com.au> <56D76F12.6060006@opensource.altera.com> <56D77289.6080808@opensource.altera.com> <56D77646.7060804@denx.de> <56D9B2A1.6050708@opensource.altera.com> <56D9DBF9.7070805@denx.de> <1458569143.2112.10.camel@altera.com> <1458575153.2112.14.camel@altera.com> <1458745223.1850.6.camel@altera.com> <56F2B852.3090507@denx.de> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, Mar 23, 2016 at 10:37 AM, Stefan Roese wrote: > > I can't really comment on the USB problem, as I've only seen this > d-cache / S-bit problem with SPI NOR flash. This is because I've never > really used USB on this platform intensively. But I'm nearly 100% > sure, that all changes that add some delays (or debug printfs) > resulting in a "working solution", either in the USB case or the SPI > NOR case, are just papering over the real problem. > After a quick chat with Mark Rutland here at ELC, he alluded that there could be a problem with the PL310 interfering with the L1 DCACHE. I won't be able to try it until I get back, but perhaps somebody can test turning off the PL310? --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -78,7 +78,6 @@ * Cache */ #define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS Dinh