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* [PATCH v3] drm/amdgpu: Restore msix after FLR
@ 2021-06-25  6:44 Peng Ju Zhou
  2021-06-29 10:38 ` Zhou, Peng Ju
  2021-06-29 14:27 ` Alex Deucher
  0 siblings, 2 replies; 5+ messages in thread
From: Peng Ju Zhou @ 2021-06-25  6:44 UTC (permalink / raw)
  To: amd-gfx; +Cc: Emily.Deng

From: "Emily.Deng" <Emily.Deng@amd.com>

After FLR, the msix will be cleared, so need to re-enable it.

Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 90f50561b43a..26e63cb5d8d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -277,6 +277,16 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev)
 	return true;
 }
 
+void amdgpu_restore_msix(struct amdgpu_device *adev)
+{
+	u16 ctrl;
+
+	pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
+	ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
+	pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
+	ctrl |= PCI_MSIX_FLAGS_ENABLE;
+	pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
+}
 /**
  * amdgpu_irq_init - initialize interrupt handling
  *
@@ -558,6 +568,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
 {
 	int i, j, k;
 
+	amdgpu_restore_msix(adev);
 	for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
 		if (!adev->irq.client[i].sources)
 			continue;
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* RE: [PATCH v3] drm/amdgpu: Restore msix after FLR
  2021-06-25  6:44 [PATCH v3] drm/amdgpu: Restore msix after FLR Peng Ju Zhou
@ 2021-06-29 10:38 ` Zhou, Peng Ju
  2021-06-29 14:27 ` Alex Deucher
  1 sibling, 0 replies; 5+ messages in thread
From: Zhou, Peng Ju @ 2021-06-29 10:38 UTC (permalink / raw)
  To: Zhou, Peng Ju, amd-gfx; +Cc: Deng, Emily

[AMD Official Use Only]

Ping


---------------------------------------------------------------------- 
BW
Pengju Zhou



> -----Original Message-----
> From: Peng Ju Zhou <PengJu.Zhou@amd.com>
> Sent: Friday, June 25, 2021 2:44 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily <Emily.Deng@amd.com>; Zhou, Peng Ju
> <PengJu.Zhou@amd.com>
> Subject: [PATCH v3] drm/amdgpu: Restore msix after FLR
> 
> From: "Emily.Deng" <Emily.Deng@amd.com>
> 
> After FLR, the msix will be cleared, so need to re-enable it.
> 
> Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 90f50561b43a..26e63cb5d8d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -277,6 +277,16 @@ static bool amdgpu_msi_ok(struct amdgpu_device
> *adev)
>  	return true;
>  }
> 
> +void amdgpu_restore_msix(struct amdgpu_device *adev) {
> +	u16 ctrl;
> +
> +	pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
> PCI_MSIX_FLAGS, &ctrl);
> +	ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
> +	pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
> PCI_MSIX_FLAGS, ctrl);
> +	ctrl |= PCI_MSIX_FLAGS_ENABLE;
> +	pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
> +PCI_MSIX_FLAGS, ctrl); }
>  /**
>   * amdgpu_irq_init - initialize interrupt handling
>   *
> @@ -558,6 +568,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
> amdgpu_device *adev)  {
>  	int i, j, k;
> 
> +	amdgpu_restore_msix(adev);
>  	for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
>  		if (!adev->irq.client[i].sources)
>  			continue;
> --
> 2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH v3] drm/amdgpu: Restore msix after FLR
  2021-06-25  6:44 [PATCH v3] drm/amdgpu: Restore msix after FLR Peng Ju Zhou
  2021-06-29 10:38 ` Zhou, Peng Ju
@ 2021-06-29 14:27 ` Alex Deucher
  2021-07-01  2:34   ` Zhou, Peng Ju
  1 sibling, 1 reply; 5+ messages in thread
From: Alex Deucher @ 2021-06-29 14:27 UTC (permalink / raw)
  To: Peng Ju Zhou; +Cc: Emily.Deng, amd-gfx list

On Fri, Jun 25, 2021 at 2:44 AM Peng Ju Zhou <PengJu.Zhou@amd.com> wrote:
>
> From: "Emily.Deng" <Emily.Deng@amd.com>
>
> After FLR, the msix will be cleared, so need to re-enable it.

Do we need to store whether we enabled msix in the first place and
then decide whether to enable it again in this case?

Alex

>
> Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 90f50561b43a..26e63cb5d8d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -277,6 +277,16 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev)
>         return true;
>  }
>
> +void amdgpu_restore_msix(struct amdgpu_device *adev)
> +{
> +       u16 ctrl;
> +
> +       pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
> +       ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
> +       pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
> +       ctrl |= PCI_MSIX_FLAGS_ENABLE;
> +       pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
> +}
>  /**
>   * amdgpu_irq_init - initialize interrupt handling
>   *
> @@ -558,6 +568,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
>  {
>         int i, j, k;
>
> +       amdgpu_restore_msix(adev);
>         for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
>                 if (!adev->irq.client[i].sources)
>                         continue;
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* RE: [PATCH v3] drm/amdgpu: Restore msix after FLR
  2021-06-29 14:27 ` Alex Deucher
@ 2021-07-01  2:34   ` Zhou, Peng Ju
  2021-07-01  2:58     ` Alex Deucher
  0 siblings, 1 reply; 5+ messages in thread
From: Zhou, Peng Ju @ 2021-07-01  2:34 UTC (permalink / raw)
  To: Alex Deucher; +Cc: Deng, Emily, amd-gfx list

[AMD Official Use Only]

Hi Alex
The function amdgpu_restore_msix is used for reset the msix during board reset(sriov reset or asic reset), it moves from host to guest, so I think a flag to indicate if msix enabled is not needed.


---------------------------------------------------------------------- 
BW
Pengju Zhou



> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Tuesday, June 29, 2021 10:28 PM
> To: Zhou, Peng Ju <PengJu.Zhou@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deng, Emily
> <Emily.Deng@amd.com>
> Subject: Re: [PATCH v3] drm/amdgpu: Restore msix after FLR
> 
> On Fri, Jun 25, 2021 at 2:44 AM Peng Ju Zhou <PengJu.Zhou@amd.com> wrote:
> >
> > From: "Emily.Deng" <Emily.Deng@amd.com>
> >
> > After FLR, the msix will be cleared, so need to re-enable it.
> 
> Do we need to store whether we enabled msix in the first place and then
> decide whether to enable it again in this case?
> 
> Alex
> 
> >
> > Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
> > Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> > index 90f50561b43a..26e63cb5d8d5 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> > @@ -277,6 +277,16 @@ static bool amdgpu_msi_ok(struct amdgpu_device
> *adev)
> >         return true;
> >  }
> >
> > +void amdgpu_restore_msix(struct amdgpu_device *adev) {
> > +       u16 ctrl;
> > +
> > +       pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
> PCI_MSIX_FLAGS, &ctrl);
> > +       ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
> > +       pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
> PCI_MSIX_FLAGS, ctrl);
> > +       ctrl |= PCI_MSIX_FLAGS_ENABLE;
> > +       pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
> > +PCI_MSIX_FLAGS, ctrl); }
> >  /**
> >   * amdgpu_irq_init - initialize interrupt handling
> >   *
> > @@ -558,6 +568,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
> > amdgpu_device *adev)  {
> >         int i, j, k;
> >
> > +       amdgpu_restore_msix(adev);
> >         for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
> >                 if (!adev->irq.client[i].sources)
> >                         continue;
> > --
> > 2.17.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfx&amp;data=04%7C01%7CPe
> >
> ngJu.Zhou%40amd.com%7C409895f80e0d43ecba3808d93b0a15fc%7C3dd8961
> fe4884
> >
> e608e11a82d994e183d%7C0%7C0%7C637605736778199787%7CUnknown%7C
> TWFpbGZsb
> >
> 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> 3D%
> >
> 7C1000&amp;sdata=w%2FgDzhoAjDraAMiyfx3XTPxx1QNff3OY%2BZWn1NYq%
> 2Ffo%3D&
> > amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH v3] drm/amdgpu: Restore msix after FLR
  2021-07-01  2:34   ` Zhou, Peng Ju
@ 2021-07-01  2:58     ` Alex Deucher
  0 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2021-07-01  2:58 UTC (permalink / raw)
  To: Zhou, Peng Ju; +Cc: Deng, Emily, amd-gfx list

On Wed, Jun 30, 2021 at 10:34 PM Zhou, Peng Ju <PengJu.Zhou@amd.com> wrote:
>
> [AMD Official Use Only]
>
> Hi Alex
> The function amdgpu_restore_msix is used for reset the msix during board reset(sriov reset or asic reset), it moves from host to guest, so I think a flag to indicate if msix enabled is not needed.
>

The function ultimately enables MSIX.  What if it was not enabled in
the first place?

Alex

>
> ----------------------------------------------------------------------
> BW
> Pengju Zhou
>
>
>
> > -----Original Message-----
> > From: Alex Deucher <alexdeucher@gmail.com>
> > Sent: Tuesday, June 29, 2021 10:28 PM
> > To: Zhou, Peng Ju <PengJu.Zhou@amd.com>
> > Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deng, Emily
> > <Emily.Deng@amd.com>
> > Subject: Re: [PATCH v3] drm/amdgpu: Restore msix after FLR
> >
> > On Fri, Jun 25, 2021 at 2:44 AM Peng Ju Zhou <PengJu.Zhou@amd.com> wrote:
> > >
> > > From: "Emily.Deng" <Emily.Deng@amd.com>
> > >
> > > After FLR, the msix will be cleared, so need to re-enable it.
> >
> > Do we need to store whether we enabled msix in the first place and then
> > decide whether to enable it again in this case?
> >
> > Alex
> >
> > >
> > > Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
> > > Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 11 +++++++++++
> > >  1 file changed, 11 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> > > index 90f50561b43a..26e63cb5d8d5 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> > > @@ -277,6 +277,16 @@ static bool amdgpu_msi_ok(struct amdgpu_device
> > *adev)
> > >         return true;
> > >  }
> > >
> > > +void amdgpu_restore_msix(struct amdgpu_device *adev) {
> > > +       u16 ctrl;
> > > +
> > > +       pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
> > PCI_MSIX_FLAGS, &ctrl);
> > > +       ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
> > > +       pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
> > PCI_MSIX_FLAGS, ctrl);
> > > +       ctrl |= PCI_MSIX_FLAGS_ENABLE;
> > > +       pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
> > > +PCI_MSIX_FLAGS, ctrl); }
> > >  /**
> > >   * amdgpu_irq_init - initialize interrupt handling
> > >   *
> > > @@ -558,6 +568,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
> > > amdgpu_device *adev)  {
> > >         int i, j, k;
> > >
> > > +       amdgpu_restore_msix(adev);
> > >         for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
> > >                 if (!adev->irq.client[i].sources)
> > >                         continue;
> > > --
> > > 2.17.1
> > >
> > > _______________________________________________
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> > gfx&amp;data=04%7C01%7CPe
> > >
> > ngJu.Zhou%40amd.com%7C409895f80e0d43ecba3808d93b0a15fc%7C3dd8961
> > fe4884
> > >
> > e608e11a82d994e183d%7C0%7C0%7C637605736778199787%7CUnknown%7C
> > TWFpbGZsb
> > >
> > 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > 3D%
> > >
> > 7C1000&amp;sdata=w%2FgDzhoAjDraAMiyfx3XTPxx1QNff3OY%2BZWn1NYq%
> > 2Ffo%3D&
> > > amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-07-01  2:58 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-25  6:44 [PATCH v3] drm/amdgpu: Restore msix after FLR Peng Ju Zhou
2021-06-29 10:38 ` Zhou, Peng Ju
2021-06-29 14:27 ` Alex Deucher
2021-07-01  2:34   ` Zhou, Peng Ju
2021-07-01  2:58     ` Alex Deucher

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