* [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
@ 2017-08-15 9:53 Huang Rui
[not found] ` <1502790786-14449-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Huang Rui @ 2017-08-15 9:53 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ken Wang
From: Ken Wang <Ken.Wang@amd.com>
Change-Id: If01e32baa903c8c35991b1517c6d8bde98f5dae2
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 68a0d40..66312d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1670,6 +1670,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
u32 tmp;
u32 rb_bufsz;
u64 rb_addr, rptr_addr, wptr_gpu_addr;
+ int r;
/* Set the write pointer delay */
WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
@@ -1729,6 +1730,17 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
/* start the ring */
gfx_v9_0_cp_gfx_start(adev);
+
+ r = amdgpu_ring_alloc(ring, 3);
+ if (r) {
+ return r;
+ }
+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+ tmp = ((2 << 28) | (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
+ amdgpu_ring_write(ring, tmp);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_commit(ring);
+
ring->ready = true;
return 0;
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
[not found] ` <1502790786-14449-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
@ 2017-08-15 15:02 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2017-08-15 15:02 UTC (permalink / raw)
To: Huang Rui; +Cc: Ken Wang, amd-gfx list
On Tue, Aug 15, 2017 at 5:53 AM, Huang Rui <ray.huang@amd.com> wrote:
> From: Ken Wang <Ken.Wang@amd.com>
>
Please include a better description. Something like "this register
has no default value and needs to be initialized by the driver."
> Change-Id: If01e32baa903c8c35991b1517c6d8bde98f5dae2
> Signed-off-by: Ken Wang <Ken.Wang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 68a0d40..66312d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1670,6 +1670,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
> u32 tmp;
> u32 rb_bufsz;
> u64 rb_addr, rptr_addr, wptr_gpu_addr;
> + int r;
>
> /* Set the write pointer delay */
> WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
> @@ -1729,6 +1730,17 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
>
> /* start the ring */
> gfx_v9_0_cp_gfx_start(adev);
> +
> + r = amdgpu_ring_alloc(ring, 3);
> + if (r) {
> + return r;
> + }
> + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
> + tmp = ((2 << 28) | (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
Why the 2 << 28? What is that for?
> + amdgpu_ring_write(ring, tmp);
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_commit(ring);
> +
Please either add this to the existing packet sequence in
gfx_v9_0_cp_gfx_start() or update the register via mmio in
gfx_v9_0_gpu_init().
Alex
> ring->ready = true;
>
> return 0;
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
[not found] ` <1502948583-25827-1-git-send-email-ken.wang-5C7GfCeVMHo@public.gmane.org>
2017-08-17 5:58 ` Zhang, Hawking
@ 2017-08-17 12:41 ` Deucher, Alexander
1 sibling, 0 replies; 8+ messages in thread
From: Deucher, Alexander @ 2017-08-17 12:41 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wang, Ken
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ken.wang@amd.com
> Sent: Thursday, August 17, 2017 1:43 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wang, Ken
> Subject: [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
>
Please include a better description. E.g.,
mmVGT_INDEX_TYPE has no default value, need to make sure it's initialized when gfx is initialized.
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> From: Ken Wang <Ken.Wang@amd.com>
>
> Change-Id: If01e32baa903c8c35991b1517c6d8bde98f5dae2
> Signed-off-by: Ken Wang <Ken.Wang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++--
> drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 +
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 1f6a34b..e183b50 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1615,7 +1615,7 @@ static int gfx_v9_0_cp_gfx_start(struct
> amdgpu_device *adev)
> struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
> const struct cs_section_def *sect = NULL;
> const struct cs_extent_def *ext = NULL;
> - int r, i;
> + int r, i, tmp;
>
> /* init the CP */
> WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev-
> >gfx.config.max_hw_contexts - 1);
> @@ -1623,7 +1623,7 @@ static int gfx_v9_0_cp_gfx_start(struct
> amdgpu_device *adev)
>
> gfx_v9_0_cp_gfx_enable(adev, true);
>
> - r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
> + r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
> if (r) {
> DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
> return r;
> @@ -1661,6 +1661,12 @@ static int gfx_v9_0_cp_gfx_start(struct
> amdgpu_device *adev)
> amdgpu_ring_write(ring, 0x8000);
> amdgpu_ring_write(ring, 0x8000);
>
> + amdgpu_ring_write(ring,
> PACKET3(PACKET3_SET_UCONFIG_REG,1));
> + tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
> + (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) -
> PACKET3_SET_UCONFIG_REG_START));
> + amdgpu_ring_write(ring, tmp);
> + amdgpu_ring_write(ring, 0);
> +
> amdgpu_ring_commit(ring);
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h
> b/drivers/gpu/drm/amd/amdgpu/soc15d.h
> index ab94201..3b29827 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
> @@ -250,6 +250,7 @@
> #define PACKET3_SET_UCONFIG_REG 0x79
> #define PACKET3_SET_UCONFIG_REG_START
> 0x0000c000
> #define PACKET3_SET_UCONFIG_REG_END
> 0x0000c400
> +#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE
> (2 << 28)
> #define PACKET3_SCRATCH_RAM_WRITE 0x7D
> #define PACKET3_SCRATCH_RAM_READ 0x7E
> #define PACKET3_LOAD_CONST_RAM 0x80
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
[not found] ` <1502948583-25827-1-git-send-email-ken.wang-5C7GfCeVMHo@public.gmane.org>
@ 2017-08-17 5:58 ` Zhang, Hawking
2017-08-17 12:41 ` Deucher, Alexander
1 sibling, 0 replies; 8+ messages in thread
From: Zhang, Hawking @ 2017-08-17 5:58 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wang, Ken
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Regards,
Hawking
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of ken.wang@amd.com
Sent: Thursday, August 17, 2017 13:43
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Ken <Ken.Wang@amd.com>
Subject: [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
From: Ken Wang <Ken.Wang@amd.com>
Change-Id: If01e32baa903c8c35991b1517c6d8bde98f5dae2
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++--
drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1f6a34b..e183b50 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1615,7 +1615,7 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
const struct cs_section_def *sect = NULL;
const struct cs_extent_def *ext = NULL;
- int r, i;
+ int r, i, tmp;
/* init the CP */
WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); @@ -1623,7 +1623,7 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
gfx_v9_0_cp_gfx_enable(adev, true);
- r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
+ r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
if (r) {
DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
return r;
@@ -1661,6 +1661,12 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
amdgpu_ring_write(ring, 0x8000);
amdgpu_ring_write(ring, 0x8000);
+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
+ tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
+ amdgpu_ring_write(ring, tmp);
+ amdgpu_ring_write(ring, 0);
+
amdgpu_ring_commit(ring);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h
index ab94201..3b29827 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15d.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
@@ -250,6 +250,7 @@
#define PACKET3_SET_UCONFIG_REG 0x79
#define PACKET3_SET_UCONFIG_REG_START 0x0000c000
#define PACKET3_SET_UCONFIG_REG_END 0x0000c400
+#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28)
#define PACKET3_SCRATCH_RAM_WRITE 0x7D
#define PACKET3_SCRATCH_RAM_READ 0x7E
#define PACKET3_LOAD_CONST_RAM 0x80
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
@ 2017-08-17 5:43 ken.wang-5C7GfCeVMHo
[not found] ` <1502948583-25827-1-git-send-email-ken.wang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: ken.wang-5C7GfCeVMHo @ 2017-08-17 5:43 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ken Wang
From: Ken Wang <Ken.Wang@amd.com>
Change-Id: If01e32baa903c8c35991b1517c6d8bde98f5dae2
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++--
drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1f6a34b..e183b50 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1615,7 +1615,7 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
const struct cs_section_def *sect = NULL;
const struct cs_extent_def *ext = NULL;
- int r, i;
+ int r, i, tmp;
/* init the CP */
WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
@@ -1623,7 +1623,7 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
gfx_v9_0_cp_gfx_enable(adev, true);
- r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
+ r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
if (r) {
DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
return r;
@@ -1661,6 +1661,12 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
amdgpu_ring_write(ring, 0x8000);
amdgpu_ring_write(ring, 0x8000);
+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
+ tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
+ amdgpu_ring_write(ring, tmp);
+ amdgpu_ring_write(ring, 0);
+
amdgpu_ring_commit(ring);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h
index ab94201..3b29827 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15d.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
@@ -250,6 +250,7 @@
#define PACKET3_SET_UCONFIG_REG 0x79
#define PACKET3_SET_UCONFIG_REG_START 0x0000c000
#define PACKET3_SET_UCONFIG_REG_END 0x0000c400
+#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28)
#define PACKET3_SCRATCH_RAM_WRITE 0x7D
#define PACKET3_SCRATCH_RAM_READ 0x7E
#define PACKET3_LOAD_CONST_RAM 0x80
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
@ 2017-08-15 9:38 Ken Wang
0 siblings, 0 replies; 8+ messages in thread
From: Ken Wang @ 2017-08-15 9:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ken Wang
Change-Id: If01e32baa903c8c35991b1517c6d8bde98f5dae2
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 68a0d40..66312d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1670,6 +1670,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
u32 tmp;
u32 rb_bufsz;
u64 rb_addr, rptr_addr, wptr_gpu_addr;
+ int r;
/* Set the write pointer delay */
WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
@@ -1729,6 +1730,17 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
/* start the ring */
gfx_v9_0_cp_gfx_start(adev);
+
+ r = amdgpu_ring_alloc(ring, 3);
+ if (r) {
+ return r;
+ }
+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+ tmp = ((2 << 28) | (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
+ amdgpu_ring_write(ring, tmp);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_commit(ring);
+
ring->ready = true;
return 0;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
@ 2017-08-15 9:33 Ken Wang
0 siblings, 0 replies; 8+ messages in thread
From: Ken Wang @ 2017-08-15 9:33 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ken Wang
Change-Id: If01e32baa903c8c35991b1517c6d8bde98f5dae2
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 68a0d40..f47ee5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -230,6 +230,7 @@ static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
r = -EINVAL;
}
amdgpu_gfx_scratch_free(adev, scratch);
+
return r;
}
@@ -1670,6 +1671,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
u32 tmp;
u32 rb_bufsz;
u64 rb_addr, rptr_addr, wptr_gpu_addr;
+ int r;
/* Set the write pointer delay */
WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
@@ -1729,6 +1731,17 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
/* start the ring */
gfx_v9_0_cp_gfx_start(adev);
+
+ r = amdgpu_ring_alloc(ring, 3);
+ if (r) {
+ return r;
+ }
+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+ tmp = ((2 << 28) | (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
+ amdgpu_ring_write(ring, tmp);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_commit(ring);
+
ring->ready = true;
return 0;
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test
@ 2017-08-15 9:19 Ken Wang
0 siblings, 0 replies; 8+ messages in thread
From: Ken Wang @ 2017-08-15 9:19 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ken Wang
Change-Id: If01e32baa903c8c35991b1517c6d8bde98f5dae2
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 68a0d40..f47ee5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -230,6 +230,7 @@ static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
r = -EINVAL;
}
amdgpu_gfx_scratch_free(adev, scratch);
+
return r;
}
@@ -1670,6 +1671,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
u32 tmp;
u32 rb_bufsz;
u64 rb_addr, rptr_addr, wptr_gpu_addr;
+ int r;
/* Set the write pointer delay */
WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
@@ -1729,6 +1731,17 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
/* start the ring */
gfx_v9_0_cp_gfx_start(adev);
+
+ r = amdgpu_ring_alloc(ring, 3);
+ if (r) {
+ return r;
+ }
+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+ tmp = ((2 << 28) | (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
+ amdgpu_ring_write(ring, tmp);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_commit(ring);
+
ring->ready = true;
return 0;
--
2.7.4
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2017-08-15 9:53 [PATCH] drm/amdgpu: fix vega10 graphic hang issue in S3 test Huang Rui
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2017-08-15 15:02 ` Alex Deucher
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2017-08-17 5:43 ken.wang-5C7GfCeVMHo
[not found] ` <1502948583-25827-1-git-send-email-ken.wang-5C7GfCeVMHo@public.gmane.org>
2017-08-17 5:58 ` Zhang, Hawking
2017-08-17 12:41 ` Deucher, Alexander
2017-08-15 9:38 Ken Wang
2017-08-15 9:33 Ken Wang
2017-08-15 9:19 Ken Wang
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