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charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Thu, May 13, 2021 at 1:32 AM Luben Tuikov wrote: > > On QUERY2 IOCTL don't query counts of correctable > and uncorrectable errors, since when RAS is > enabled and supported on Vega20 server boards, > this takes insurmountably long time, in O(n^3), > which slows the system down to the point of it > being unusable when we have GUI up. > > Fixes: ae363a212b14 ("drm/amdgpu: Add a new flag to AMDGPU_CTX_OP_QUERY_STATE2") > Cc: Alexander Deucher > Cc: stable@vger.kernel.org > Signed-off-by: Luben Tuikov Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 16 ---------------- > 1 file changed, 16 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > index 01fe60fedcbe..e1557020c49d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > @@ -337,7 +337,6 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev, > { > struct amdgpu_ctx *ctx; > struct amdgpu_ctx_mgr *mgr; > - unsigned long ras_counter; > > if (!fpriv) > return -EINVAL; > @@ -362,21 +361,6 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev, > if (atomic_read(&ctx->guilty)) > out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; > > - /*query ue count*/ > - ras_counter = amdgpu_ras_query_error_count(adev, false); > - /*ras counter is monotonic increasing*/ > - if (ras_counter != ctx->ras_counter_ue) { > - out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE; > - ctx->ras_counter_ue = ras_counter; > - } > - > - /*query ce count*/ > - ras_counter = amdgpu_ras_query_error_count(adev, true); > - if (ras_counter != ctx->ras_counter_ce) { > - out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE; > - ctx->ras_counter_ce = ras_counter; > - } > - > mutex_unlock(&mgr->lock); > return 0; > } > -- > 2.31.1.527.g2d677e5b15 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D4CCC433B4 for ; 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Thu, 13 May 2021 12:41:40 -0700 (PDT) MIME-Version: 1.0 References: <20210513053233.116683-1-luben.tuikov@amd.com> In-Reply-To: <20210513053233.116683-1-luben.tuikov@amd.com> From: Alex Deucher Date: Thu, 13 May 2021 15:41:29 -0400 Message-ID: Subject: Re: [PATCH 1/2] drm/amdgpu: Don't query CE and UE errors To: Luben Tuikov X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Deucher , "for 3.8" , amd-gfx list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Thu, May 13, 2021 at 1:32 AM Luben Tuikov wrote: > > On QUERY2 IOCTL don't query counts of correctable > and uncorrectable errors, since when RAS is > enabled and supported on Vega20 server boards, > this takes insurmountably long time, in O(n^3), > which slows the system down to the point of it > being unusable when we have GUI up. > > Fixes: ae363a212b14 ("drm/amdgpu: Add a new flag to AMDGPU_CTX_OP_QUERY_STATE2") > Cc: Alexander Deucher > Cc: stable@vger.kernel.org > Signed-off-by: Luben Tuikov Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 16 ---------------- > 1 file changed, 16 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > index 01fe60fedcbe..e1557020c49d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > @@ -337,7 +337,6 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev, > { > struct amdgpu_ctx *ctx; > struct amdgpu_ctx_mgr *mgr; > - unsigned long ras_counter; > > if (!fpriv) > return -EINVAL; > @@ -362,21 +361,6 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev, > if (atomic_read(&ctx->guilty)) > out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; > > - /*query ue count*/ > - ras_counter = amdgpu_ras_query_error_count(adev, false); > - /*ras counter is monotonic increasing*/ > - if (ras_counter != ctx->ras_counter_ue) { > - out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE; > - ctx->ras_counter_ue = ras_counter; > - } > - > - /*query ce count*/ > - ras_counter = amdgpu_ras_query_error_count(adev, true); > - if (ras_counter != ctx->ras_counter_ce) { > - out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE; > - ctx->ras_counter_ce = ras_counter; > - } > - > mutex_unlock(&mgr->lock); > return 0; > } > -- > 2.31.1.527.g2d677e5b15 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx