From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw0-f195.google.com ([209.85.161.195]:33955 "EHLO mail-yw0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752021AbcFQRvp convert rfc822-to-8bit (ORCPT ); Fri, 17 Jun 2016 13:51:45 -0400 Received: by mail-yw0-f195.google.com with SMTP id b75so9608382ywe.1 for ; Fri, 17 Jun 2016 10:51:44 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <5764352D.2070206@gmail.com> References: <1466173225-14886-1-git-send-email-alexander.deucher@amd.com> <576417EC.7010300@gmail.com> <5764352D.2070206@gmail.com> From: Alex Deucher Date: Fri, 17 Jun 2016 13:51:43 -0400 Message-ID: Subject: Re: [amd-gfx] [PATCH] drm/amdgpu: fix num_rbs exposed to userspace To: =?UTF-8?Q?Nicolai_H=C3=A4hnle?= Cc: amd-gfx@lists.freedesktop.org, Alex Deucher , "for 3.8" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: stable-owner@vger.kernel.org List-ID: On Fri, Jun 17, 2016 at 1:36 PM, Nicolai Hähnle wrote: > On 17.06.2016 17:37, Alex Deucher wrote: >> >> On Fri, Jun 17, 2016 at 11:31 AM, Nicolai Hähnle >> wrote: >>> >>> On 17.06.2016 16:20, Alex Deucher wrote: >>>> >>>> >>>> This was accidently broken for harvest cards when the >>>> code was refactored for Polaris support. >>>> >>>> Signed-off-by: Alex Deucher >>>> Cc: stable@vger.kernel.org >>>> --- >>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- >>>> 1 file changed, 1 insertion(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>>> index 9ab28ca..e5c22cd 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>>> @@ -459,7 +459,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, >>>> void *data, struct drm_file >>>> dev_info.max_memory_clock = >>>> adev->pm.default_mclk >>>> * 10; >>>> } >>>> dev_info.enabled_rb_pipes_mask = >>>> adev->gfx.config.backend_enable_mask; >>>> - dev_info.num_rb_pipes = adev->gfx.config.num_rbs; >>>> + dev_info.num_rb_pipes = >>>> adev->gfx.config.max_backends_per_se; >>> >>> >>> >>> At a glance, that looks suspicious to me. num_rb_pipes becomes rb_pipes >>> in >>> libdrmm and then num_render_backends. We divide num_render_backends by >>> the >>> number of SEs * SHs in radeonsi. >>> >>> In a nutshell, radeonsi expects this to be the total number of RBs >>> (including disabled/harvested ones). >> >> >> Right. that's what this patch does. >> adev->gfx.config.max_backends_per_se is the total number of RBs per SE >> available on the asic. adev->gfx.config.num_rbs is the total number of >> enabled RBs (max - disabled). For non-harvest cards, they are the >> same. > > > But the total number of RBs is different from the total number of RBs per > SE... > Whoops yes. New patch sent. Alex > Nicolai > > >> >> Alex >> >>> >>> Nicolai >>> >>> >>>> dev_info.num_hw_gfx_contexts = >>>> adev->gfx.config.max_hw_contexts; >>>> dev_info._pad = 0; >>>> dev_info.ids_flags = 0; >>>> >>> >