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From: Alex Deucher <alexdeucher@gmail.com>
To: Peng Ju Zhou <PengJu.Zhou@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH v4 01/16] drm/amdgpu: Indirect register access for Navi12 sriov - new internal macro
Date: Fri, 14 May 2021 17:13:04 -0400	[thread overview]
Message-ID: <CADnq5_PFVXw3q9OhNxBthG-7M61H9_rJv+1=if43ukC1UA8h_g@mail.gmail.com> (raw)
In-Reply-To: <20210514072706.4264-1-PengJu.Zhou@amd.com>

On Fri, May 14, 2021 at 3:27 AM Peng Ju Zhou <PengJu.Zhou@amd.com> wrote:
>
> Change RLCG/SOC15 register access interface to triage
> GC/MMHUB access from MMIO to RLCG.
>
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>

I think patches 1-4, 16 need to be squashed together to avoid breaking
the build.  Please also provide a description of how the new macros
work in the patch description.  Describe how the reworked macros
properly handle sending GC and MMHUB accesses via the RLC rather than
via some other mechanism.  It's really hard to follow the macro logic.

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/soc15_common.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index 14bd794bbea6..9b18e19f4c73 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -27,6 +27,16 @@
>  /* Register Access Macros */
>  #define SOC15_REG_OFFSET(ip, inst, reg)        (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>
> +#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
> +       ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
> +        adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
> +        WREG32(reg, value))
> +
> +#define __RREG32_SOC15_RLC__(reg, flag, hwip) \
> +       ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
> +        adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
> +        RREG32(reg))
> +
>  #define WREG32_FIELD15(ip, idx, reg, field, val)       \
>         WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,  \
>         (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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      parent reply	other threads:[~2021-05-14 21:13 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-14  7:26 [PATCH v4 01/16] drm/amdgpu: Indirect register access for Navi12 sriov - new internal macro Peng Ju Zhou
2021-05-14  7:26 ` [PATCH v4 02/16] drm/amdgpu: Indirect register access for Navi12 sriov - SOC15 macro Peng Ju Zhou
2021-05-14  7:26 ` [PATCH v4 03/16] drm/amdgpu: Indirect register access for Navi12 sriov - RLC interface Peng Ju Zhou
2021-05-14  7:26 ` [PATCH v4 04/16] drm/amdgpu: Indirect register access for Navi12 sriov - GFX v10 Peng Ju Zhou
2021-05-14  7:26 ` [PATCH v4 05/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10* Peng Ju Zhou
2021-05-14  7:26 ` [PATCH v4 06/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10* Peng Ju Zhou
2021-05-14  7:26 ` [PATCH v4 07/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c Peng Ju Zhou
2021-05-14  7:26 ` [PATCH v4 08/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file sdma_v5* Peng Ju Zhou
2021-05-14  7:26 ` [PATCH v4 09/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c Peng Ju Zhou
2021-05-14  7:27 ` [PATCH v4 10/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c Peng Ju Zhou
2021-05-14  7:27 ` [PATCH v4 11/16] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2* Peng Ju Zhou
2021-05-14  7:27 ` [PATCH v4 12/16] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers Peng Ju Zhou
2021-05-14 19:54   ` Alex Deucher
2021-05-14  7:27 ` [PATCH v4 13/16] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV Peng Ju Zhou
2021-05-14 20:00   ` Alex Deucher
2021-05-14  7:27 ` [PATCH v4 14/16] drm/amdgpu: Skip the program of GRBM_CAM* " Peng Ju Zhou
2021-05-14 19:55   ` Alex Deucher
2021-05-14  7:27 ` [PATCH v4 15/16] drm/amdgpu: Refine the error report when flush tlb Peng Ju Zhou
2021-05-14 19:53   ` Alex Deucher
2021-05-14  7:27 ` [PATCH v4 16/16] drm/amdgpu: Update gfx_v9 rlcg interface Peng Ju Zhou
2021-05-14  7:56   ` Zhou, Peng Ju
2021-05-14 21:05   ` Alex Deucher
2021-05-14 21:13 ` Alex Deucher [this message]

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