From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex Deucher Subject: Re: [PATCH 6/6] drm/radeon: Fix the definition of RADEON_BUF_SWAP_32BIT Date: Wed, 13 Jul 2011 10:47:43 -0400 Message-ID: References: <1310538506.4968.96.camel@pasglop> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-iw0-f177.google.com (mail-iw0-f177.google.com [209.85.214.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 60FD99F3AC for ; Wed, 13 Jul 2011 07:47:44 -0700 (PDT) Received: by iwn35 with SMTP id 35so6571784iwn.36 for ; Wed, 13 Jul 2011 07:47:43 -0700 (PDT) In-Reply-To: <1310538506.4968.96.camel@pasglop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Benjamin Herrenschmidt Cc: xorg-driver-ati@lists.x.org, dri-devel@lists.freedesktop.org, Cedric Cano List-Id: dri-devel@lists.freedesktop.org On Wed, Jul 13, 2011 at 2:28 AM, Benjamin Herrenschmidt wrote: > (Note that this is duplicated under various other names such > as R600_BUF_SWAP_32BIT etc...). At least now all the definitions > agree. > > Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Alex Deucher > --- > > (resent adding dri-devel to the CC list to hit patchwork) > > =A0drivers/gpu/drm/radeon/radeon_reg.h | =A0 =A02 +- > =A01 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon= /radeon_reg.h > index ec93a75..0828add1 100644 > --- a/drivers/gpu/drm/radeon/radeon_reg.h > +++ b/drivers/gpu/drm/radeon/radeon_reg.h > @@ -3293,7 +3293,7 @@ > =A0# =A0 =A0 =A0define RADEON_RB_BUFSZ_MASK =A0 =A0 =A0 =A0 =A0 =A0 (0x3f= << 0) > =A0# =A0 =A0 =A0define RADEON_RB_BLKSZ_SHIFT =A0 =A0 =A0 =A0 =A0 =A08 > =A0# =A0 =A0 =A0define RADEON_RB_BLKSZ_MASK =A0 =A0 =A0 =A0 =A0 =A0 (0x3f= << 8) > -# =A0 =A0 =A0define RADEON_BUF_SWAP_32BIT =A0 =A0 =A0 =A0 =A0 =A0(1 << 1= 7) > +# =A0 =A0 =A0define RADEON_BUF_SWAP_32BIT =A0 =A0 =A0 =A0 =A0 =A0(2 << 1= 6) > =A0# =A0 =A0 =A0define RADEON_MAX_FETCH_SHIFT =A0 =A0 =A0 =A0 =A0 18 > =A0# =A0 =A0 =A0define RADEON_MAX_FETCH_MASK =A0 =A0 =A0 =A0 =A0 =A0(0x3 = << 18) > =A0# =A0 =A0 =A0define RADEON_RB_NO_UPDATE =A0 =A0 =A0 =A0 =A0 =A0 =A0(1 = << 27) > > > >