From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex Deucher Subject: Re: [PATCH] drm/radeon: Add RADEON_GEM_CPU_ACCESS BO creation flag Date: Mon, 8 Sep 2014 13:36:27 -0400 Message-ID: References: <1409208961-7322-1-git-send-email-michel@daenzer.net> <53FEEEF4.7030401@vodafone.de> <53FFDB6B.5050105@daenzer.net> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary=089e0149c9ea2a917f0502914220 Return-path: In-Reply-To: <53FFDB6B.5050105@daenzer.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: mesa-dev-bounces@lists.freedesktop.org Sender: "mesa-dev" To: =?UTF-8?Q?Michel_D=C3=A4nzer?= Cc: "mesa-dev@lists.freedesktop.org" , Maling list - DRI developers List-Id: dri-devel@lists.freedesktop.org --089e0149c9ea2a917f0502914220 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Thu, Aug 28, 2014 at 9:46 PM, Michel D=C3=A4nzer wr= ote: > On 29.08.2014 00:01, Alex Deucher wrote: >> On Thu, Aug 28, 2014 at 4:57 AM, Christian K=C3=B6nig >> wrote: >>> Am 28.08.2014 um 08:56 schrieb Michel D=C3=A4nzer: >>> >>>> From: Michel D=C3=A4nzer >>>> >>>> This flag is a hint that userspace expects the BO to be accessed by th= e >>>> CPU. We can use that hint to prevent such BOs from ever being stored i= n >>>> the CPU inaccessible part of VRAM. >>>> >>>> Signed-off-by: Michel D=C3=A4nzer >>> >>> >>> This patch is Reviewed-by: Christian K=C3=B6nig >> >> Applied to my -next tree. > > Thanks! > > >>> I think we need a similar negative flags as well, e.g. >>> RADEON_GEM_NO_CPU_ACCESS. >>> >>> This way we can stop forcing buffers into the visible VRAM while pinnin= g >>> them for scanout. >> >> How about the attached patch? > > [...] > >> diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/ra= deon/radeon_object.c >> index 09b039a..b71e8e0 100644 >> --- a/drivers/gpu/drm/radeon/radeon_object.c >> +++ b/drivers/gpu/drm/radeon/radeon_object.c >> @@ -314,10 +314,14 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo,= u32 domain, u64 max_offset, >> unsigned lpfn =3D 0; >> >> /* force to pin into visible video ram */ >> - if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) >> - lpfn =3D bo->rdev->mc.visible_vram_size >> PAGE_SH= IFT; >> - else >> + if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) { >> + if (bo->flags & RADEON_GEM_NO_CPU_ACCESS) >> + lpfn =3D bo->rdev->mc.real_vram_size >> PA= GE_SHIFT; >> + else >> + lpfn =3D bo->rdev->mc.visible_vram_size >>= PAGE_SHIFT; > > lpfn can be left at 0 if RADEON_GEM_NO_CPU_ACCESS is set, so this can > be simplified to: > > if (!(bo->flags & RADEON_GEM_NO_CPU_ACCESS)) > lpfn =3D bo->rdev->mc.visible_vram_size >= > PAGE_SHIFT; > > >> diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm= .h >> index f755f20..d2346fd 100644 >> --- a/include/uapi/drm/radeon_drm.h >> +++ b/include/uapi/drm/radeon_drm.h >> @@ -803,6 +803,8 @@ struct drm_radeon_gem_info { >> #define RADEON_GEM_GTT_WC (1 << 2) >> /* BO is expected to be accessed by the CPU */ >> #define RADEON_GEM_CPU_ACCESS (1 << 3) >> +/* BO is expected to not be accessed by the CPU */ >> +#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) > > I'd use stronger wording for this, e.g. > > /* CPU access is not expected to work for this BO */ Updated version with comments integrated. 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