I was thinking of the traditional Xen PV mode in which page table pages are write protected from guest meddling and PTE modifications are audited by the hypervisor (ptwr_emulated_update() these days, still?).

Without software shadows or paging to e.g. an EPT, native PV loads the actual CR3 pointing to a write protected page table tree. When the cr3 is loaded, the hardware walker will want to set A and D bits in PTEs -- is this action immune to the write protection in the page table pages themselves? Or do we take emulation faults on these updates as well?

Thanks