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From: Stephen Boyd <swboyd@chromium.org>
To: Prasad Malisetty <pmaliset@codeaurora.org>,
	agross@kernel.org, bhelgaas@google.com,
	bjorn.andersson@linaro.org, lorenzo.pieralisi@arm.com,
	robh+dt@kernel.org, svarbanov@mm-sol.com
Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
	dianders@chromium.org, mka@chromium.org, vbadigan@codeaurora.org,
	sallenki@codeaurora.org, manivannan.sadhasivam@linaro.org,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH v10 3/5] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
Date: Mon, 4 Oct 2021 21:10:49 -0400	[thread overview]
Message-ID: <CAE-0n50WXwP52YM9k6YrPwNWs+KCuODg=mnmROUUPvdwvRxEsw@mail.gmail.com> (raw)
In-Reply-To: <1633376488-545-4-git-send-email-pmaliset@codeaurora.org>

Quoting Prasad Malisetty (2021-10-04 12:41:26)
> Enable PCIe controller and PHY for sc7280 IDP board.
> Add specific NVMe GPIO entries for SKU1 and SKU2 support.
>
> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7280-idp.dts  |  8 +++++
>  arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 51 ++++++++++++++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/sc7280-idp2.dts |  8 +++++
>  3 files changed, 67 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> index 272d5ca..b416f3d 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> @@ -462,6 +491,28 @@
>  };
>
>  &tlmm {
> +       nvme_pwren_pin: nvme-pwren-pin {

pin is sort of redundant but OK. It would be simpler without the pin
postfix.

> +               function = "gpio";
> +               bias-pull-up;

Why is there a bias pull up on this enable pin? I'd expect to see a
bias-disable as this is an output pin and there's no need for a pull.

> +       };
> +
> +       pcie1_reset_n: pcie1-reset-n {
> +               pins = "gpio2";
> +               function = "gpio";
> +
> +               drive-strength = <16>;

Why such a strong drive strength?

> +               output-low;
> +               bias-disable;
> +       };
> +
> +       pcie1_wake_n: pcie1-wake-n {
> +               pins = "gpio3";
> +               function = "gpio";
> +
> +               drive-strength = <2>;
> +               bias-pull-up;
> +       };
> +
>         qup_uart7_sleep_cts: qup-uart7-sleep-cts {
>                 pins = "gpio28";
>                 function = "gpio";

  reply	other threads:[~2021-10-05  1:10 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-04 19:41 [PATCH v10 0/5] Add DT bindings and DT nodes for PCIe and PHY in SC7280 Prasad Malisetty
2021-10-04 19:41 ` [PATCH v10 1/5] dt-bindings: pci: qcom: Document PCIe bindings for SC7280 Prasad Malisetty
2021-10-04 19:41 ` [PATCH v10 2/5] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes Prasad Malisetty
2021-10-05  1:11   ` Stephen Boyd
2021-10-04 19:41 ` [PATCH v10 3/5] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board Prasad Malisetty
2021-10-05  1:10   ` Stephen Boyd [this message]
2021-10-04 19:41 ` [PATCH v10 4/5] PCI: qcom: Add a flag in match data along with ops Prasad Malisetty
2021-10-05  1:13   ` Stephen Boyd
2021-10-04 19:41 ` [PATCH v10 5/5] PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280 Prasad Malisetty

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