Re: [PATCH v4 1/2] arm64: dts: qcom: sc7280: Add USB related nodes

[Stephen Boyd <swboyd@chromium.org>]

Quoting Sandeep Maheswaram (2021-06-04 04:03:37)
> Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> ---
> changed usb3-phy to lanes in qmp phy node as it was causing probe failure.
>
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 149 +++++++++++++++++++++++++++++++++++
>  1 file changed, 149 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 0b6f119..d70d5fb 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -973,6 +973,110 @@
>                         };
>                 };
>
> +               usb_1_hsphy: phy@88e3000 {
> +                       compatible = "qcom,sc7280-usb-hs-phy",
> +                                    "qcom,usb-snps-hs-7nm-phy";
> +                       reg = <0 0x088e3000 0 0x400>;
> +                       status = "disabled";
> +                       #phy-cells = <0>;
> +
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>;
> +                       clock-names = "ref";
> +
> +                       resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> +               };
> +
> +               usb_2_hsphy: phy@88e4000 {
> +                       compatible = "qcom,sc7280-usb-hs-phy",
> +                                    "qcom,usb-snps-hs-7nm-phy";
> +                       reg = <0 0x088e4000 0 0x400>;
> +                       status = "disabled";
> +                       #phy-cells = <0>;
> +
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>;
> +                       clock-names = "ref";
> +
> +                       resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
> +               };
> +
> +               usb_1_qmpphy: phy-wrapper@88e9000 {
> +                       compatible = "qcom,sm8250-qmp-usb3-phy";

Is this another combo usb/dp phy?

> +                       reg = <0 0x088e9000 0 0x200>,
> +                             <0 0x088e8000 0 0x20>;
> +                       reg-names = "reg-base", "dp_com";
> +                       status = "disabled";
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +
> +                       clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> +                                <&rpmhcc RPMH_CXO_CLK>,
> +                                <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> +                       clock-names = "aux", "ref_clk_src", "com_aux";
> +
> +                       resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,

This makes me think yes. In which case, can we put the final node in
place instead of having to tack on DP phy at a later time?

> +                                <&gcc GCC_USB3_PHY_PRIM_BCR>;
> +                       reset-names = "phy", "common";
> +
> +                       usb_1_ssphy: lanes@88e9200 {

phy@88e9200?

> +                               reg = <0 0x088e9200 0 0x200>,
> +                                     <0 0x088e9400 0 0x200>,
> +                                     <0 0x088e9c00 0 0x400>,
> +                                     <0 0x088e9600 0 0x200>,
> +                                     <0 0x088e9800 0 0x200>,
> +                                     <0 0x088e9a00 0 0x100>;
> +                               #phy-cells = <0>;
> +                               #clock-cells = <1>;
> +                               clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> +                               clock-names = "pipe0";
> +                               clock-output-names = "usb3_phy_pipe_clk_src";
> +                       };
> +               };
> +