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To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Content-Type: multipart/alternative; boundary="000000000000db89c905b85be38d" Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=luoyonggang@gmail.com; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: luoyonggang@gmail.com Cc: Thomas Monjalon , qemu-ppc@nongnu.org, qemu-level , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000db89c905b85be38d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Jan 8, 2021 at 5:54 AM C=C3=A9dric Le Goater wrote: > > On 1/7/21 8:14 PM, =E7=BD=97=E5=8B=87=E5=88=9A(Yonggang Luo) wrote: > > This is the first patch,: > > It's store MSR bits differntly for different rfi instructions: > > [Qemu-devel] [PATCH] target-ppc: fix RFI by clearing some bits of MSR > > https://lists.gnu.org/archive/html/qemu-devel/2010-05/msg02999.html < https://lists.gnu.org/archive/html/qemu-devel/2010-05/msg02999.html> > > Comes from target-ppc: fix RFI by clearing some bits of MSR > > SHA-1: c3d420ead1aee9fcfd12be11cbdf6b1620134773 > > target-ppc/op_helper.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > ``` > > diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c > > index 8f2ee986bb..3c3aa60bc3 100644 > > --- a/target-ppc/op_helper.c > > +++ b/target-ppc/op_helper.c > > @@ -1646,20 +1646,20 @@ static inline void do_rfi(target_ulong nip, target_ulong msr, > > void helper_rfi (void) > > { > > do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1], > > - ~((target_ulong)0x0), 1); > > + ~((target_ulong)0x783F0000), 1); > > } > > > > #if defined(TARGET_PPC64) > > void helper_rfid (void) > > { > > do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1], > > - ~((target_ulong)0x0), 0); > > + ~((target_ulong)0x783F0000), 0); > > } > > > > void helper_hrfid (void) > > { > > do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1], > > - ~((target_ulong)0x0), 0); > > + ~((target_ulong)0x783F0000), 0); > > } > > #endif > > #endif > > ``` > > > > This is the second patch,: > > it's remove the parameter `target_ulong msrm, int keep_msrh` > > Comes from ppc: Fix rfi/rfid/hrfi/... emulation > > SHA-1: a2e71b28e832346409efc795ecd1f0a2bcb705a3 > > ``` > > target-ppc/excp_helper.c | 51 +++++++++++++++++++----------------------------- > > 1 file changed, 20 insertions(+), 31 deletions(-) > > > > diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c > > index 30e960e30b..aa0b63f4b0 100644 > > --- a/target-ppc/excp_helper.c > > +++ b/target-ppc/excp_helper.c > > @@ -922,25 +922,20 @@ void helper_store_msr(CPUPPCState *env, target_ulong val) > > } > > } > > > > -static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr, > > - target_ulong msrm, int keep_msrh) > > +static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) > > { > > CPUState *cs =3D CPU(ppc_env_get_cpu(env)); > > > > + /* MSR:POW cannot be set by any form of rfi */ > > + msr &=3D ~(1ULL << MSR_POW); > > + > > #if defined(TARGET_PPC64) > > - if (msr_is_64bit(env, msr)) { > > - nip =3D (uint64_t)nip; > > - msr &=3D (uint64_t)msrm; > > - } else { > > + /* Switching to 32-bit ? Crop the nip */ > > + if (!msr_is_64bit(env, msr)) { > > nip =3D (uint32_t)nip; > > - msr =3D (uint32_t)(msr & msrm); > > - if (keep_msrh) { > > - msr |=3D env->msr & ~((uint64_t)0xFFFFFFFF); > > - } > > } > > #else > > nip =3D (uint32_t)nip; > > - msr &=3D (uint32_t)msrm; > > #endif > > /* XXX: beware: this is false if VLE is supported */ > > env->nip =3D nip & ~((target_ulong)0x00000003); > > @@ -959,26 +954,24 @@ static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr, > > > > void helper_rfi(CPUPPCState *env) > > { > > - if (env->excp_model =3D=3D POWERPC_EXCP_BOOKE) { > > - do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1], > > - ~((target_ulong)0), 0); > > - } else { > > - do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1], > > - ~((target_ulong)0x783F0000), 1); > > - } > > + do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful)= ; > > } > > > > +#define MSR_BOOK3S_MASK > > #if defined(TARGET_PPC64) > > void helper_rfid(CPUPPCState *env) > > { > > - do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1], > > - ~((target_ulong)0x783F0000), 0); > > + /* The architeture defines a number of rules for which bits > > + * can change but in practice, we handle this in hreg_store_msr() > > + * which will be called by do_rfi(), so there is no need to filter > > + * here > > + */ > > + do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); > > } > > > > void helper_hrfid(CPUPPCState *env) > > { > > - do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1], > > - ~((target_ulong)0x783F0000), 0); > > + do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); > > } > > #endif > > > > @@ -986,28 +979,24 @@ void helper_hrfid(CPUPPCState *env) > > /* Embedded PowerPC specific helpers */ > > void helper_40x_rfci(CPUPPCState *env) > > { > > - do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3], > > - ~((target_ulong)0xFFFF0000), 0); > > + do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]); > > } > > > > void helper_rfci(CPUPPCState *env) > > { > > - do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], > > - ~((target_ulong)0), 0); > > + do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]); > > } > > > > void helper_rfdi(CPUPPCState *env) > > { > > /* FIXME: choose CSRR1 or DSRR1 based on cpu type */ > > - do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1], > > - ~((target_ulong)0), 0); > > + do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]); > > } > > > > void helper_rfmci(CPUPPCState *env) > > { > > /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */ > > - do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]= , > > - ~((target_ulong)0), 0); > > + do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); > > } > > #endif > > > > @@ -1045,7 +1034,7 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2, > > > > void helper_rfsvc(CPUPPCState *env) > > { > > - do_rfi(env, env->lr, env->ctr, 0x0000FFFF, 0); > > + do_rfi(env, env->lr, env->ctr & 0x0000FFFF); > > } > > > > /* Embedded.Processor Control */ > > ``` > > > > And of cause, the second patch fixes some problem, but also cause new problem, > > how to implement these instruction properly? > > What are the new problems ? Before this patch, VxWorks can working, but after this, VxWorks can not boot anymore. > > C. > > > > > > > > > -- > > =E6=AD=A4=E8=87=B4 > > =E7=A4=BC > > =E7=BD=97=E5=8B=87=E5=88=9A > > Yours > > sincerely, > > Yonggang Luo > -- =E6=AD=A4=E8=87=B4 =E7=A4=BC =E7=BD=97=E5=8B=87=E5=88=9A Yours sincerely, Yonggang Luo --000000000000db89c905b85be38d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Fri, Jan 8, 2021 at 5:54 AM C=C3=A9dric Le Goat= er <clg@kaod.org> wrote:
><= br>> On 1/7/21 8:14 PM, =E7=BD=97=E5=8B=87=E5=88=9A(Yonggang Luo) wrote:=
> > This is the first patch,:
> > It's store MSR bit= s differntly for different rfi instructions:
> > [Qemu-devel] [PAT= CH] target-ppc: fix RFI by clearing some bits of MSR
> > ht= tps://lists.gnu.org/archive/html/qemu-devel/2010-05/msg02999.html <<= a href=3D"https://lists.gnu.org/archive/html/qemu-devel/2010-05/msg02999.ht= ml">https://lists.gnu.org/archive/html/qemu-devel/2010-05/msg02999.html= >
> > Comes from =C2=A0target-ppc: fix RFI by clearing some bit= s of MSR
> > SHA-1: c3d420ead1aee9fcfd12be11cbdf6b1620134773
&g= t; > =C2=A0target-ppc/op_helper.c | 6 +++---
> > =C2=A01 file c= hanged, 3 insertions(+), 3 deletions(-)
> > ```
> > diff = --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> > index = 8f2ee986bb..3c3aa60bc3 100644
> > --- a/target-ppc/op_helper.c
= > > +++ b/target-ppc/op_helper.c
> > @@ -1646,20 +1646,20 @@= static inline void do_rfi(target_ulong nip, target_ulong msr,
> >= =C2=A0void helper_rfi (void)
> > =C2=A0{
> > =C2=A0 =C2= =A0 =C2=A0do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
> >= - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~((target_ulong)0x0), 1);
> >= ; + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~((target_ulong)0x783F0000), 1);
= > > =C2=A0}
> > =C2=A0
> > =C2=A0#if defined(TARGET= _PPC64)
> > =C2=A0void helper_rfid (void)
> > =C2=A0{
= > > =C2=A0 =C2=A0 =C2=A0do_rfi(env->spr[SPR_SRR0], env->spr[SPR= _SRR1],
> > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~((target_ulong)0= x0), 0);
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~((target_ulong)= 0x783F0000), 0);
> > =C2=A0}
> > =C2=A0
> > =C2= =A0void helper_hrfid (void)
> > =C2=A0{
> > =C2=A0 =C2=A0= =C2=A0do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
> > = - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~((target_ulong)0x0), 0);
> >= + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~((target_ulong)0x783F0000), 0);
&= gt; > =C2=A0}
> > =C2=A0#endif
> > =C2=A0#endif
>= ; > ```
> >
> > This is the second patch,:
> >= ; it's remove the parameter =C2=A0`target_ulong msrm, int keep_msrh`> > Comes from ppc: Fix rfi/rfid/hrfi/... emulation
> > SHA= -1: a2e71b28e832346409efc795ecd1f0a2bcb705a3
> > ```
> > = =C2=A0target-ppc/excp_helper.c | 51 +++++++++++++++++++--------------------= ---------
> > =C2=A01 file changed, 20 insertions(+), 31 deletions= (-)
> >
> > diff --git a/target-ppc/excp_helper.c b/targe= t-ppc/excp_helper.c
> > index 30e960e30b..aa0b63f4b0 100644
>= ; > --- a/target-ppc/excp_helper.c
> > +++ b/target-ppc/excp_he= lper.c
> > @@ -922,25 +922,20 @@ void helper_store_msr(CPUPPCState= *env, target_ulong val)
> > =C2=A0 =C2=A0 =C2=A0}
> > = =C2=A0}
> > =C2=A0
> > -static inline void do_rfi(CPUPPCS= tate *env, target_ulong nip, target_ulong msr,
> > - =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0target_ulong msrm, int keep_msrh)
> > +static inline void do_rf= i(CPUPPCState *env, target_ulong nip, target_ulong msr)
> > =C2=A0= {
> > =C2=A0 =C2=A0 =C2=A0CPUState *cs =3D CPU(ppc_env_get_cpu(env= ));
> > =C2=A0
> > + =C2=A0 =C2=A0/* MSR:POW cannot be se= t by any form of rfi */
> > + =C2=A0 =C2=A0msr &=3D ~(1ULL <= ;< MSR_POW);
> > +
> > =C2=A0#if defined(TARGET_PPC64)=
> > - =C2=A0 =C2=A0if (msr_is_64bit(env, msr)) {
> > - = =C2=A0 =C2=A0 =C2=A0 =C2=A0nip =3D (uint64_t)nip;
> > - =C2=A0 =C2= =A0 =C2=A0 =C2=A0msr &=3D (uint64_t)msrm;
> > - =C2=A0 =C2=A0}= else {
> > + =C2=A0 =C2=A0/* Switching to 32-bit ? Crop the nip *= /
> > + =C2=A0 =C2=A0if (!msr_is_64bit(env, msr)) {
> > = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0nip =3D (uint32_t)nip;
> > - =C2= =A0 =C2=A0 =C2=A0 =C2=A0msr =3D (uint32_t)(msr & msrm);
> > - = =C2=A0 =C2=A0 =C2=A0 =C2=A0if (keep_msrh) {
> > - =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0msr |=3D env->msr & ~((uint64_t)0xFFFFFFF= F);
> > - =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> > =C2=A0 =C2=A0 = =C2=A0}
> > =C2=A0#else
> > =C2=A0 =C2=A0 =C2=A0nip =3D (= uint32_t)nip;
> > - =C2=A0 =C2=A0msr &=3D (uint32_t)msrm;
&= gt; > =C2=A0#endif
> > =C2=A0 =C2=A0 =C2=A0/* XXX: beware: this= is false if VLE is supported */
> > =C2=A0 =C2=A0 =C2=A0env->n= ip =3D nip & ~((target_ulong)0x00000003);
> > @@ -959,26 +954,= 24 @@ static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_= ulong msr,
> > =C2=A0
> > =C2=A0void helper_rfi(CPUPPCSta= te *env)
> > =C2=A0{
> > - =C2=A0 =C2=A0if (env->excp_= model =3D=3D POWERPC_EXCP_BOOKE) {
> > - =C2=A0 =C2=A0 =C2=A0 =C2= =A0do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1],
> > -= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~((target_ulong)0), 0);> > - =C2=A0 =C2=A0} else {
> > - =C2=A0 =C2=A0 =C2=A0 =C2= =A0do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1],
> > -= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~((target_ulong)0x783F000= 0), 1);
> > - =C2=A0 =C2=A0}
> > + =C2=A0 =C2=A0do_rfi(en= v, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
>= ; > =C2=A0}
> > =C2=A0
> > +#define MSR_BOOK3S_MASK> > =C2=A0#if defined(TARGET_PPC64)
> > =C2=A0void helper_r= fid(CPUPPCState *env)
> > =C2=A0{
> > - =C2=A0 =C2=A0do_r= fi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1],
> > - =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~((target_ulong)0x783F0000), 0);
> > = + =C2=A0 =C2=A0/* The architeture defines a number of rules for which bits<= br>> > + =C2=A0 =C2=A0 * can change but in practice, we handle this i= n hreg_store_msr()
> > + =C2=A0 =C2=A0 * which will be called by d= o_rfi(), so there is no need to filter
> > + =C2=A0 =C2=A0 * here<= br>> > + =C2=A0 =C2=A0 */
> > + =C2=A0 =C2=A0do_rfi(env, env= ->spr[SPR_SRR0], env->spr[SPR_SRR1]);
> > =C2=A0}
> &g= t; =C2=A0
> > =C2=A0void helper_hrfid(CPUPPCState *env)
> &g= t; =C2=A0{
> > - =C2=A0 =C2=A0do_rfi(env, env->spr[SPR_HSRR0], = env->spr[SPR_HSRR1],
> > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~= ((target_ulong)0x783F0000), 0);
> > + =C2=A0 =C2=A0do_rfi(env, env= ->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
> > =C2=A0}
> = > =C2=A0#endif
> > =C2=A0
> > @@ -986,28 +979,24 @@ vo= id helper_hrfid(CPUPPCState *env)
> > =C2=A0/* Embedded PowerPC sp= ecific helpers */
> > =C2=A0void helper_40x_rfci(CPUPPCState *env)=
> > =C2=A0{
> > - =C2=A0 =C2=A0do_rfi(env, env->spr[S= PR_40x_SRR2], env->spr[SPR_40x_SRR3],
> > - =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 ~((target_ulong)0xFFFF0000), 0);
> > + =C2=A0 = =C2=A0do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]);> > =C2=A0}
> > =C2=A0
> > =C2=A0void helper_rfci(= CPUPPCState *env)
> > =C2=A0{
> > - =C2=A0 =C2=A0do_rfi(e= nv, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
> >= ; - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~((target_ulong)0), 0);
> >= + =C2=A0 =C2=A0do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_B= OOKE_CSRR1]);
> > =C2=A0}
> > =C2=A0
> > =C2=A0v= oid helper_rfdi(CPUPPCState *env)
> > =C2=A0{
> > =C2=A0 = =C2=A0 =C2=A0/* FIXME: choose CSRR1 or DSRR1 based on cpu type */
> &= gt; - =C2=A0 =C2=A0do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SP= R_BOOKE_DSRR1],
> > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~((target= _ulong)0), 0);
> > + =C2=A0 =C2=A0do_rfi(env, env->spr[SPR_BOOK= E_DSRR0], env->spr[SPR_BOOKE_DSRR1]);
> > =C2=A0}
> > = =C2=A0
> > =C2=A0void helper_rfmci(CPUPPCState *env)
> > = =C2=A0{
> > =C2=A0 =C2=A0 =C2=A0/* FIXME: choose CSRR1 or MCSRR1 b= ased on cpu type */
> > - =C2=A0 =C2=A0do_rfi(env, env->spr[SPR= _BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1],
> > - =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 ~((target_ulong)0), 0);
> > + =C2=A0 =C2=A0d= o_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);> > =C2=A0}
> > =C2=A0#endif
> > =C2=A0
> &= gt; @@ -1045,7 +1034,7 @@ void helper_td(CPUPPCState *env, target_ulong arg= 1, target_ulong arg2,
> > =C2=A0
> > =C2=A0void helper_rf= svc(CPUPPCState *env)
> > =C2=A0{
> > - =C2=A0 =C2=A0do_r= fi(env, env->lr, env->ctr, 0x0000FFFF, 0);
> > + =C2=A0 =C2= =A0do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
> > =C2= =A0}
> > =C2=A0
> > =C2=A0/* Embedded.Processor Control *= /
> > ```
> >
> > And of cause, the second patch= fixes some problem, but also cause new problem,
> > how to implem= ent these instruction properly?
>
> What are the new problems = =C2=A0?
Before this patch, VxWorks can working, but after this, VxWorks= can not boot anymore.

>
> C.
>
> >> >
> >
> > --
> > =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0=E6=AD=A4=E8=87=B4
> > =E7=A4=BC
> > =E7=BD= =97=E5=8B=87=E5=88=9A
> > Yours
> > =C2=A0 =C2=A0 sincere= ly,
> > Yonggang Luo
>


--
=C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0=E6=AD=A4=E8=87=B4
=E7=A4=BC
=E7=BD=97=E5=8B=87=E5=88= =9A
Yours
=C2=A0 =C2=A0 sincerely,
Yonggang Luo
--000000000000db89c905b85be38d--