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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: luoyonggang@gmail.com Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000022f56405b2992360 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Oct 27, 2020 at 4:44 AM Peter Maydell wrote: > > Ping for review ? > Maybe nobody can review this, anyway, is that possible add a test case for this? I found https://github.com/oxidecomputer/qemu-systick-bug are simple enough= . > thanks > -- PMM > > On Thu, 15 Oct 2020 at 16:18, Peter Maydell wrote: > > > > This patch series rewrites our implementation of the armv7m systick > > timer to use ptimers. > > > > The armv7m systick timer is a 24-bit decrementing, wrap-on-zero, > > clear-on-write counter. Our current implementation has various bugs > > and dubious workarounds in it (for instance see > > https://bugs.launchpad.net/qemu/+bug/1872237). > > > > We have an implementation of a simple decrementing counter and we put > > a lot of effort into making sure it handles the interesting corner > > cases (like "spend a cycle at 0 before reloading"), so rather than > > trying to fix these all over again in systick's hand-rolled countdown > > code it's much simpler to just rewrite it to use a ptimer. > > > > Unfortunately this is a migration compatibility break, which will > > affect all M-profile boards. > > > > Among other bugs, this fixes > > https://bugs.launchpad.net/qemu/+bug/1872237 : now writes to SYST_CVR > > when the timer is enabled correctly do nothing; when the timer is > > enabled via SYST_CSR.ENABLE, the ptimer code will (because of > > POLICY_NO_IMMEDIATE_RELOAD) arrange that after one timer tick the > > counter is reloaded from SYST_RVR and then counts down from there, as > > the architecture requires. > > > > Side note: the trace from the test program in LP1872237 won't look > > quite like it does on the hardware: under QEMU the "waiting for 1000 > > ms" debug printing generally reports a SYST_CVR value of 0. This is > > because QEMU's emulated CPU is comparatively fast and our systick has a > > hard-wired value of 1MHz for the frequency of the 'external reference > > clock', which means that execution of the guest code reaches "read > > SYST_CVR" before the first tick of the timer clock after enabling of > > the timer (which is where the reload of SYST_CVR from SYST_RVR is > > required). The exception is the first iteration, where the time QEMU > > takes to translate the guest code is enough that the timer tick > > happens before the register read. You can also get the timer tick to > > win the race by fiddling around with the -icount option (which > > effectively is slowing down the emulated CPU speed). > > > > Some day we should model both the 'system_clock_scale' (ie the CPU > > clock frequency) and the 'external reference clock' as QEMU clock > > source/sinks so that board code can specify the correct reference > > clock frequency. > > > > Patch 1 is a minor tweak to the ptimer code to suppress a spurious > > warning message for the "timer callback function disabled the ptimer" > > case, which the systick timer uses. Patch 2 is the actual > > conversion. > > > > thanks > > -- PMM > > > > > > Peter Maydell (2): > > hw/core/ptimer: Support ptimer being disabled by timer callback > > hw/timer/armv7m_systick: Rewrite to use ptimers > > > > include/hw/timer/armv7m_systick.h | 3 +- > > hw/core/ptimer.c | 4 + > > hw/timer/armv7m_systick.c | 124 +++++++++++++----------------- > > 3 files changed, 58 insertions(+), 73 deletions(-) > > > > -- > > 2.20.1 > > > -- =E6=AD=A4=E8=87=B4 =E7=A4=BC =E7=BD=97=E5=8B=87=E5=88=9A Yours sincerely, Yonggang Luo --00000000000022f56405b2992360 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Tue, Oct 27, 2020 at 4:44 AM Peter Maydell <= peter.maydell@linaro.org>= ; wrote:
>
> Ping for review ?
>
Maybe nobody can rev= iew this, anyway, is that possible add a test case for this?
I fo= und=C2=A0http= s://github.com/oxidecomputer/qemu-systick-bug are simple enough.
>= ; thanks
> -- PMM
>
> On Thu, 15 Oct 2020 at 16:18, Peter= Maydell <peter.maydell@lina= ro.org> wrote:
> >
> > This patch series rewrites = our implementation of the armv7m systick
> > timer to use ptimers.=
> >
> > The armv7m systick timer is a 24-bit decrementin= g, wrap-on-zero,
> > clear-on-write counter.=C2=A0 Our current imp= lementation has various bugs
> > and dubious workarounds in it (fo= r instance see
> > https://bugs.launchpad.net/qemu/+bug/1872237).
> >> > We have an implementation of a simple decrementing counter and = we put
> > a lot of effort into making sure it handles the interes= ting corner
> > cases (like "spend a cycle at 0 before reload= ing"), so rather than
> > trying to fix these all over again = in systick's hand-rolled countdown
> > code it's much simp= ler to just rewrite it to use a ptimer.
> >
> > Unfortuna= tely this is a migration compatibility break, which will
> > affec= t all M-profile boards.
> >
> > Among other bugs, this fi= xes
> > h= ttps://bugs.launchpad.net/qemu/+bug/1872237 : now writes to SYST_CVR> > when the timer is enabled correctly do nothing; when the timer i= s
> > enabled via SYST_CSR.ENABLE, the ptimer code will (because o= f
> > POLICY_NO_IMMEDIATE_RELOAD) arrange that after one timer tic= k the
> > counter is reloaded from SYST_RVR and then counts down f= rom there, as
> > the architecture requires.
> >
> = > Side note: the trace from the test program in LP1872237 won't look=
> > quite like it does on the hardware: under QEMU the "wait= ing for 1000
> > ms" debug printing generally reports a SYST_= CVR value of 0.=C2=A0 This is
> > because QEMU's emulated CPU = is comparatively fast and our systick has a
> > hard-wired value o= f 1MHz for the frequency of the 'external reference
> > clock&= #39;, which means that execution of the guest code reaches "read
&g= t; > SYST_CVR" before the first tick of the timer clock after enabl= ing of
> > the timer (which is where the reload of SYST_CVR from S= YST_RVR is
> > required).=C2=A0 The exception is the first iterati= on, where the time QEMU
> > takes to translate the guest code is e= nough that the timer tick
> > happens before the register read.=C2= =A0 You can also get the timer tick to
> > win the race by fiddlin= g around with the -icount option (which
> > effectively is slowing= down the emulated CPU speed).
> >
> > Some day we should= model both the 'system_clock_scale' (ie the CPU
> > clock= frequency) and the 'external reference clock' as QEMU clock
>= ; > source/sinks so that board code can specify the correct reference> > clock frequency.
> >
> > Patch 1 is a minor tw= eak to the ptimer code to suppress a spurious
> > warning message = for the "timer callback function disabled the ptimer"
> >= ; case, which the systick timer uses.=C2=A0 Patch 2 is the actual
> &= gt; conversion.
> >
> > thanks
> > -- PMM
>= ; >
> >
> > Peter Maydell (2):
> > =C2=A0 hw/= core/ptimer: Support ptimer being disabled by timer callback
> > = =C2=A0 hw/timer/armv7m_systick: Rewrite to use ptimers
> >
>= > =C2=A0include/hw/timer/armv7m_systick.h | =C2=A0 3 +-
> > = =C2=A0hw/core/ptimer.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0| =C2=A0 4 +
> > =C2=A0hw/timer/armv7m_systick.c =C2=A0 = =C2=A0 =C2=A0 =C2=A0 | 124 +++++++++++++-----------------
> > =C2= =A03 files changed, 58 insertions(+), 73 deletions(-)
> >
> = > --
> > 2.20.1
> >
>


--
=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0=E6=AD=A4=E8=87=B4
=E7=A4=BC
=E7=BD=97=E5= =8B=87=E5=88=9A
Yours
=C2=A0 =C2=A0 sincerely,
Yonggang Luo
<= /div> --00000000000022f56405b2992360--