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Date: Wed, 4 Feb 2015 22:29:07 -0800
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From: Scott Feldman <sfeldma@gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v5 03/10] rocker: add register programming
	guide
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To: Stefan Hajnoczi <stefanha@gmail.com>
Cc: =?UTF-8?B?SmnFmcOtIFDDrXJrbw==?= <jiri@resnulli.us>, Roopa Prabhu <roopa@cumulusnetworks.com>, john fastabend <john.fastabend@gmail.com>, QEMU Developers <qemu-devel@nongnu.org>, David Ahern <dsahern@gmail.com>, Paolo Bonzini <pbonzini@redhat.com>, "jasowang@redhat.com" <jasowang@redhat.com>

On Mon, Feb 2, 2015 at 8:19 AM, Stefan Hajnoczi <stefanha@gmail.com> wrote:
> On Thu, Jan 22, 2015 at 12:03:52AM -0800, sfeldma@gmail.com wrote:
>> +SECTION 7: Switch Control
>> +=========================
>> +
>> +This section covers switch-wide register settings.
>> +
>> +Control
>> +-------
>> +
>> +This register is used for low level control of the switch.
>> +
>> +     CONTROL: offset 0x0300, 32-bit, (W)
>> +
>> +     bit     name            description
>> +     ------------------------------------------------------------------------
>> +     [0]     CONTROL_RESET   If set, device will perform reset
>
> This doesn't block the patch series, but I have a question:
>
> Reset is not defined.
>
> What exactly gets reset?

The internal structures for the device would get reset to a power-on
state.  In rockers case, the flow tables would be cleared and the desc
rings would be reset.

>
> How does the CPU detect that the device has completed the reset
> procedure?  Is this supposed to be synchronous?  If yes, is that a good
> idea (i.e. hopefully resetting doesn't involve any blocking operations
> or operations that take a long time)?

Ya, in this case we want the reset to be non-blocking and synchronous.