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[209.85.208.174]) by smtp.gmail.com with ESMTPSA id j20sm720083lfe.181.2020.10.01.14.50.03 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 01 Oct 2020 14:50:03 -0700 (PDT) Received: by mail-lj1-f174.google.com with SMTP id u4so112776ljd.10 for ; Thu, 01 Oct 2020 14:50:03 -0700 (PDT) X-Received: by 2002:a2e:6f0d:: with SMTP id k13mr2752865ljc.250.1601589002954; Thu, 01 Oct 2020 14:50:02 -0700 (PDT) MIME-Version: 1.0 References: <20200929205807.2360405-1-evgreen@chromium.org> <20200929135741.3.I1bb1b0e94be3b792804e08831d6a55481e162d63@changeid> <8f467220-3ac8-c8fc-33fe-8d86904571fe@linaro.org> In-Reply-To: From: Evan Green Date: Thu, 1 Oct 2020 14:49:26 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 3/3] nvmem: qfprom: Don't touch certain fuses To: Srinivas Kandagatla Cc: Rob Herring , Bjorn Andersson , Douglas Anderson , Stephen Boyd , LKML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 1, 2020 at 9:30 AM Srinivas Kandagatla wrote: > > > > On 01/10/2020 17:27, Evan Green wrote: > > On Thu, Oct 1, 2020 at 7:17 AM Srinivas Kandagatla > > wrote: > >> > >> Hi Evan, > >> > >> On 29/09/2020 21:58, Evan Green wrote: > >>> Some fuse ranges are protected by the XPU such that the AP cannot > >>> access them. Attempting to do so causes an SError. Use the newly > >>> introduced per-soc compatible string to attach the set of regions > >>> we should not access. Then tiptoe around those regions. > >>> > >> > >> This is a generic feature that can be used by any nvmem provider, can > >> you move this logic to nvmem core instead of having it in qfprom! > > > > Sure! I'd prefer to keep this data in the driver for now rather than > Ofcourse these can come from driver directly based on compatible! > > > trying to define DT bindings for the keepout zones. So then I'll pass > > in my keepout array via struct nvmem_config at registration time, and > > then the core can handle the keepout logic instead of qfprom.c. > > > > Yes, that is inline with what am thinking of as well! Oh no, I realized this isn't nearly as beautiful when I try to move it into the core. The low level read/write interface between the nvmem core and the driver is a range. So to move this into the core I'd have to implement all the overlap computation logic to potentially break up a read into several small reads in cases where there are many little keepout ranges. It was much simpler when I could just check each byte offset individually, and because I was doing it in this one rarely-used driver I could make that performance tradeoff without much penalty. I could do all range/overlap handling if you want, but it'll be a bigger change, and I worry my driver would be the only one to end up using it. What do you think? -Evan > > > 00srini > > -Evan > >