From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6A20C4338F for ; Fri, 6 Aug 2021 03:41:16 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1421A606A5 for ; Fri, 6 Aug 2021 03:41:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1421A606A5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:38252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBqjS-0006AS-UP for qemu-devel@archiver.kernel.org; Thu, 05 Aug 2021 23:41:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBqim-000544-Is; Thu, 05 Aug 2021 23:40:32 -0400 Received: from mail-yb1-xb33.google.com ([2607:f8b0:4864:20::b33]:38756) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mBqil-0001Hk-05; Thu, 05 Aug 2021 23:40:32 -0400 Received: by mail-yb1-xb33.google.com with SMTP id c137so12430984ybf.5; Thu, 05 Aug 2021 20:40:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=weAPN+ydW2028eD7P9mR7SZE9Wn5X1XG4WLPLPEGvPM=; b=PuKaHG8IHIKS3aMEdndLq25ncovGYYkenT1/l6lHjp/OLzuugYdawFXg7SeTXt6x91 NgpH0Dics4cxaVv/emjtAqkfFK88j6bCHjqq5WGZKUzCQvdCdJFV/0rGk7dFNT9+q9NJ bTGR9yPl3ICSqcCLJVRyoxf8pS9u9tP+nbs/1DTRUYZuCHNt/xsH8k6bXxYocpJbN1hc svRPQ8YDF/L07v7ZfVJIJusnRqyLZhgFB+VixZhaDC7AMtiscEbsvSgiO2ro2OVcFP4D 4DYGIL4jaYFpatapXsf6aYJVm6V1ndYgUdInwmRYylfVOff3SFHBjU9HXrGl+N33VIyW TEug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=weAPN+ydW2028eD7P9mR7SZE9Wn5X1XG4WLPLPEGvPM=; b=tuklVxZ7nOVTmenhEqO3S9NhBygxJ+YsNnEYaK+7kYclBsbFdSZEW84GHWmr0dEFGK jWMGjeEkmilhcGyEtMQP1vb4gvre2PGK+I2DLiUw9qpIo6eXJRF7jP8/0RzMVMzQncK5 uxnVhJ6TwVlY1EniM9m+w98gDFsz0eZMSjA3xbOdXQvAZ28gse7Khayw6cur4I+9HhPh rXpT94pYANYELaasWxZZeRciriT7nuB8bmPM7d/yzJnRmIeHNzC/nvC4m/iEj+0F+G/8 sSPC29mZXAqc0YpJviKlo11QxcDSo9g5skghdcJ4ufYqt7z9iylKspZTJgsCo14b/uxa j7Ig== X-Gm-Message-State: AOAM533+FtE7NOlxCBqdJdT6RVrvkQilAscK2BCEJgUZCXZzCKHQGnIi NXI3Y8UXDO80XN37yKSN7fhfsnSOAA5ELuZddeo= X-Google-Smtp-Source: ABdhPJz4xy8f0WYoumC2JWIopzFXnWAavm8cRFrTyQXVspN3We0xzETo099SdyrlMnDE4/PyeUikDElAPY3VrI5K3FA= X-Received: by 2002:a25:be09:: with SMTP id h9mr10747260ybk.239.1628221229577; Thu, 05 Aug 2021 20:40:29 -0700 (PDT) MIME-Version: 1.0 References: <20210805175626.11573-1-ruinland@andestech.com> <20210805175626.11573-4-ruinland@andestech.com> In-Reply-To: <20210805175626.11573-4-ruinland@andestech.com> From: Bin Meng Date: Fri, 6 Aug 2021 11:40:18 +0800 Message-ID: Subject: Re: [RFC PATCH v4 3/4] Adding Andes AX25 and A25 CPU model To: Ruinland Chuan-Tzu Tsai , Alistair Francis Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b33; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wangjunqiang , Bin Meng , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , Dylan Jhong Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Aug 6, 2021 at 2:00 AM Ruinland Chuan-Tzu Tsai wrote: > > From: Ruinalnd ChuanTzu Tsai > > Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without The latest RISC-V core from Andes is AX45 and A45. Should we just support the latest one? > enhanced features (yet). > > Signed-off-by: Dylan Jhong > --- > target/riscv/cpu.c | 16 ++++++++++++++++ > target/riscv/cpu.h | 2 ++ > 2 files changed, 18 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 3a638b5..9eb1e3a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -182,6 +182,13 @@ static void rv64_base_cpu_init(Object *obj) > set_misa(env, RV64); > } > > +static void ax25_cpu_init(Object *obj) nits: for name consistency, should be rv64_andes_ax25_cpu_init() > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > + > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -235,6 +242,13 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > set_resetvec(env, DEFAULT_RSTVEC); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > + > +static void a25_cpu_init(Object *obj) nits: rv32_andes_a25_cpu_init() > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > #endif > > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > @@ -726,8 +740,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_A25, a25_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_AX25, ax25_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), > #endif > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 52df9bb..bd79d63 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -37,6 +37,8 @@ > #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > +#define TYPE_RISCV_CPU_A25 RISCV_CPU_TYPE_NAME("andes-a25") > +#define TYPE_RISCV_CPU_AX25 RISCV_CPU_TYPE_NAME("andes-ax25") > #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") Regards, Bin From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mBqin-00056F-Os for mharc-qemu-riscv@gnu.org; Thu, 05 Aug 2021 23:40:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBqim-000544-Is; Thu, 05 Aug 2021 23:40:32 -0400 Received: from mail-yb1-xb33.google.com ([2607:f8b0:4864:20::b33]:38756) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mBqil-0001Hk-05; Thu, 05 Aug 2021 23:40:32 -0400 Received: by mail-yb1-xb33.google.com with SMTP id c137so12430984ybf.5; Thu, 05 Aug 2021 20:40:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=weAPN+ydW2028eD7P9mR7SZE9Wn5X1XG4WLPLPEGvPM=; b=PuKaHG8IHIKS3aMEdndLq25ncovGYYkenT1/l6lHjp/OLzuugYdawFXg7SeTXt6x91 NgpH0Dics4cxaVv/emjtAqkfFK88j6bCHjqq5WGZKUzCQvdCdJFV/0rGk7dFNT9+q9NJ bTGR9yPl3ICSqcCLJVRyoxf8pS9u9tP+nbs/1DTRUYZuCHNt/xsH8k6bXxYocpJbN1hc svRPQ8YDF/L07v7ZfVJIJusnRqyLZhgFB+VixZhaDC7AMtiscEbsvSgiO2ro2OVcFP4D 4DYGIL4jaYFpatapXsf6aYJVm6V1ndYgUdInwmRYylfVOff3SFHBjU9HXrGl+N33VIyW TEug== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b33; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Aug 2021 03:40:32 -0000 On Fri, Aug 6, 2021 at 2:00 AM Ruinland Chuan-Tzu Tsai wrote: > > From: Ruinalnd ChuanTzu Tsai > > Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without The latest RISC-V core from Andes is AX45 and A45. Should we just support the latest one? > enhanced features (yet). > > Signed-off-by: Dylan Jhong > --- > target/riscv/cpu.c | 16 ++++++++++++++++ > target/riscv/cpu.h | 2 ++ > 2 files changed, 18 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 3a638b5..9eb1e3a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -182,6 +182,13 @@ static void rv64_base_cpu_init(Object *obj) > set_misa(env, RV64); > } > > +static void ax25_cpu_init(Object *obj) nits: for name consistency, should be rv64_andes_ax25_cpu_init() > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > + > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -235,6 +242,13 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > set_resetvec(env, DEFAULT_RSTVEC); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > + > +static void a25_cpu_init(Object *obj) nits: rv32_andes_a25_cpu_init() > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > #endif > > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > @@ -726,8 +740,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_A25, a25_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_AX25, ax25_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), > #endif > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 52df9bb..bd79d63 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -37,6 +37,8 @@ > #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > +#define TYPE_RISCV_CPU_A25 RISCV_CPU_TYPE_NAME("andes-a25") > +#define TYPE_RISCV_CPU_AX25 RISCV_CPU_TYPE_NAME("andes-ax25") > #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") Regards, Bin