From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bin Meng Date: Wed, 20 Mar 2019 15:22:44 +0800 Subject: [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP. In-Reply-To: <20190319090750.8923-9-uboot@andestech.com> References: <20190319090750.8923-1-uboot@andestech.com> <20190319090750.8923-9-uboot@andestech.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Rick, On Tue, Mar 19, 2019 at 5:13 PM Andes wrote: > > From: Rick Chen > nits: remove the ending period in the commit title. > Signed-off-by: Rick Chen > Cc: Greentime Hu > --- > arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------ > arch/riscv/dts/ae350_64.dts | 47 +++++++++++++++++++++++--- > 2 files changed, 101 insertions(+), 27 deletions(-) > > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts > index 0679827..0b4d966 100644 > --- a/arch/riscv/dts/ae350_32.dts > +++ b/arch/riscv/dts/ae350_32.dts > @@ -25,17 +25,50 @@ > reg = <0>; > status = "okay"; > compatible = "riscv"; > - riscv,isa = "rv32imafdc"; > + riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0"; I am not sure what is this. Is this something approved? > + riscv,priv-major = <1>; > + riscv,priv-minor = <10>; > mmu-type = "riscv,sv32"; > clock-frequency = <60000000>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <32>; > d-cache-size = <0x8000>; > d-cache-line-size = <32>; > + next-level-cache = <&L2>; > CPU0_intc: interrupt-controller { > #interrupt-cells = <1>; > interrupt-controller; > compatible = "riscv,cpu-intc"; > }; > }; > + CPU1: cpu at 1 { > + device_type = "cpu"; > + reg = <1>; > + status = "okay"; > + compatible = "riscv"; > + riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0"; > + riscv,priv-major = <1>; > + riscv,priv-minor = <10>; > + mmu-type = "riscv,sv32"; > + clock-frequency = <60000000>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <32>; > + next-level-cache = <&L2>; > + CPU1_intc: interrupt-controller { > + #interrupt-cells = <1>; > + interrupt-controller; > + compatible = "riscv,cpu-intc"; > + }; > + }; > + > + L2: l2-cache at e0500000 { > + compatible = "cache"; > + cache-level = <2>; > + cache-size = <0x40000>; > + reg = <0x0 0xe0500000 0x0 0x40000>; > + }; > }; > > memory at 0 { > @@ -49,29 +82,29 @@ > compatible = "andestech,riscv-ae350-soc"; > ranges; > > - plic0: interrupt-controller at e4000000 { > - compatible = "riscv,plic0"; > - #address-cells = <1>; > - #interrupt-cells = <1>; > - interrupt-controller; > - reg = <0xe4000000 0x2000000>; > - riscv,ndev=<71>; > - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; > - }; > + plic0: interrupt-controller at e4000000 { > + compatible = "riscv,plic0"; > + #address-cells = <1>; > + #interrupt-cells = <1>; > + interrupt-controller; > + reg = <0xe4000000 0x2000000>; > + riscv,ndev=<71>; > + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>; > + }; > > - plic1: interrupt-controller at e6400000 { > - compatible = "riscv,plic1"; > - #address-cells = <1>; > - #interrupt-cells = <1>; > - interrupt-controller; > - reg = <0xe6400000 0x400000>; > - riscv,ndev=<1>; > - interrupts-extended = <&CPU0_intc 3>; > - }; > + plic1: interrupt-controller at e6400000 { > + compatible = "riscv,plic1"; > + #address-cells = <1>; > + #interrupt-cells = <1>; > + interrupt-controller; > + reg = <0xe6400000 0x400000>; > + riscv,ndev=<2>; > + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>; > + }; > > - plmt0 at e6000000 { > - compatible = "riscv,plmt0"; > - interrupts-extended = <&CPU0_intc 7>; > + plmt0 at e6000000 { > + compatible = "riscv,plmt0"; > + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>; > reg = <0xe6000000 0x100000>; > }; > }; > @@ -146,6 +179,10 @@ > interrupt-parent = <&plic0>; > }; > > + pmu { > + compatible = "riscv,base-pmu"; > + }; > + > virtio_mmio at fe007000 { > interrupts = <0x17 0x4>; > interrupt-parent = <0x2>; > diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts > index e48c298..3c7e152 100644 > --- a/arch/riscv/dts/ae350_64.dts > +++ b/arch/riscv/dts/ae350_64.dts > @@ -25,17 +25,50 @@ > reg = <0>; > status = "okay"; > compatible = "riscv"; > - riscv,isa = "rv64imafdc"; > + riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0"; > + riscv,priv-major = <1>; > + riscv,priv-minor = <10>; > mmu-type = "riscv,sv39"; > clock-frequency = <60000000>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <32>; > d-cache-size = <0x8000>; > d-cache-line-size = <32>; > + next-level-cache = <&L2>; > CPU0_intc: interrupt-controller { > #interrupt-cells = <1>; > interrupt-controller; > compatible = "riscv,cpu-intc"; > }; > }; > + CPU1: cpu at 1 { > + device_type = "cpu"; > + reg = <1>; > + status = "okay"; > + compatible = "riscv"; > + riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0"; > + riscv,priv-major = <1>; > + riscv,priv-minor = <10>; > + mmu-type = "riscv,sv39"; > + clock-frequency = <60000000>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <32>; > + next-level-cache = <&L2>; > + CPU1_intc: interrupt-controller { > + #interrupt-cells = <1>; > + interrupt-controller; > + compatible = "riscv,cpu-intc"; > + }; > + }; > + > + L2: l2-cache at e0500000 { > + compatible = "cache"; > + cache-level = <2>; > + cache-size = <0x40000>; > + reg = <0x0 0xe0500000 0x0 0x40000>; > + }; > }; > > memory at 0 { > @@ -56,7 +89,7 @@ > interrupt-controller; > reg = <0x0 0xe4000000 0x0 0x2000000>; > riscv,ndev=<71>; > - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; > + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>; > }; > > plic1: interrupt-controller at e6400000 { > @@ -65,13 +98,13 @@ > #interrupt-cells = <2>; > interrupt-controller; > reg = <0x0 0xe6400000 0x0 0x400000>; > - riscv,ndev=<1>; > - interrupts-extended = <&CPU0_intc 3>; > + riscv,ndev=<2>; > + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>; > }; > > plmt0 at e6000000 { > compatible = "riscv,plmt0"; > - interrupts-extended = <&CPU0_intc 7>; > + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>; > reg = <0x0 0xe6000000 0x0 0x100000>; > }; > }; > @@ -146,6 +179,10 @@ > interrupt-parent = <&plic0>; > }; > > + pmu { > + compatible = "riscv,base-pmu"; > + }; > + > virtio_mmio at fe007000 { > interrupts = <0x17 0x4>; > interrupt-parent = <0x2>; > -- Regards, Bin