From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bin Meng Date: Sat, 23 May 2015 23:50:41 +0800 Subject: [U-Boot] [PATCH] x86: baytrail: PCI is not always mapped to end of ram In-Reply-To: <1432321778-23960-1-git-send-email-andrew@bradfordembedded.com> References: <1432321778-23960-1-git-send-email-andrew@bradfordembedded.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de +Simon. Hi Andrew, On Sat, May 23, 2015 at 3:09 AM, wrote: > From: Andrew Bradford > > PCI on Intel Baytrail is mapped to 0x80000000, which is not always at > the end of SDRAM, such as when running with 4 GiB of SDRAM. The PCI bus > memory mapping must stay within low memory and so when running with > > 2 GiB of SDRAM, there is a hole in the SDRAM between 2 GiB and 4 GiB for > memory mapped IO, such as PCI. Are you saying that if we mount 4GB DDR DIMM on the MinnowMax board, the Intel FSP will only put 0~2G as system RAM space, and leave 2G~4G as PCI address and other I/Os? I see from minnowmax.h, the PCI address starts from 0xd0000000. #define CONFIG_PCI_MEM_BUS 0xd0000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS #define CONFIG_PCI_MEM_SIZE 0x10000000 #define CONFIG_PCI_PREF_BUS 0xc0000000 #define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS #define CONFIG_PCI_PREF_SIZE 0x10000000 > Signed-off-by: Andrew Bradford > --- > arch/x86/cpu/baytrail/pci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c > index 6c291f9..0a87890 100644 > --- a/arch/x86/cpu/baytrail/pci.c > +++ b/arch/x86/cpu/baytrail/pci.c > @@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose) > pci_set_region(hose->regions + 3, > 0, > 0, > - gd->ram_size, > + 0x80000000, > PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); > > hose->region_count = 4; > -- Regards, Bin