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From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH 3/3] x86: Select advanced Intel code only if allowed
Date: Thu, 25 Feb 2021 21:25:35 +0800	[thread overview]
Message-ID: <CAEUhbmUZiQv_1tgbasYkZPGgaeZYVQ-fD=8BnTkBc7OK+UyReQ@mail.gmail.com> (raw)
In-Reply-To: <20210223103542.1386572-3-sjg@chromium.org>

On Tue, Feb 23, 2021 at 6:35 PM Simon Glass <sjg@chromium.org> wrote:
>
> At present most of the Intel-specific code is built on all devices, even
> those which don't have software support for the features provided there.
>
> This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does
> not have the required features.
>
> Add a new INTEL_SOC option to control this access. This must be selected
> by SoCs that can support the required features.
>
> Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/Kconfig                | 15 +++++++++++++++
>  arch/x86/cpu/apollolake/Kconfig |  1 +
>  2 files changed, 16 insertions(+)
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index c8ce2fcb88d..b4a86f8fa05 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -1001,6 +1001,19 @@ config PCIEX_LENGTH_128MB
>  config PCIEX_LENGTH_64MB
>         bool
>
> +config INTEL_SOC
> +       bool
> +       help
> +         This is enabled on Intel SoCs that can support various advanced
> +         features such as power management (requiring asm/arch/pm.h), system
> +         agent (asm/arch/systemagent.h) and an I/O map for ACPI
> +         (asm/arch/iomap.h).
> +
> +         This cannot be seleted in a defconfig file. It must be enabled by a

typo: selected

Will fix when applying

> +         'select' in the SoC's Kconfig.
> +
> +if INTEL_SOC
> +
>  config INTEL_ACPIGEN
>         bool "Support ACPI table generation for Intel SoCs"
>         depends on ACPIGEN
> @@ -1032,4 +1045,6 @@ config INTEL_GMA_SWSMISCI
>           Select this option for Atom-based platforms which use the SWSMISCI
>           register (0xe0) rather than the SWSCI register (0xe8).
>
> +endif # INTEL_SOC
> +
>  endmenu
> diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
> index f5dbd6cbd34..590fe31dc4b 100644
> --- a/arch/x86/cpu/apollolake/Kconfig
> +++ b/arch/x86/cpu/apollolake/Kconfig
> @@ -9,6 +9,7 @@ config INTEL_APOLLOLAKE
>         select HAVE_FSP
>         select ARCH_MISC_INIT
>         select USE_CAR
> +       select INTEL_SOC
>         select INTEL_PMC
>         select TPL_X86_TSC_TIMER_NATIVE
>         select SPL_PCH_SUPPORT
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

  reply	other threads:[~2021-02-25 13:25 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-23 10:35 [PATCH 1/3] x86: Fix member check in intel_gnvs Simon Glass
2021-02-23 10:35 ` [PATCH 2/3] x86: Move INTEL_ACPIGEN to arch/x86 Simon Glass
2021-02-25 13:25   ` Bin Meng
2021-02-25 13:32     ` Bin Meng
2021-02-23 10:35 ` [PATCH 3/3] x86: Select advanced Intel code only if allowed Simon Glass
2021-02-25 13:25   ` Bin Meng [this message]
2021-02-25 13:34     ` Bin Meng
2021-02-25 13:25 ` [PATCH 1/3] x86: Fix member check in intel_gnvs Bin Meng
2021-02-25 13:31   ` Bin Meng

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