From mboxrd@z Thu Jan  1 00:00:00 1970
From: Bin Meng <bmeng.cn@gmail.com>
Date: Tue, 21 May 2019 15:55:30 +0800
Subject: [U-Boot] [PATCH] riscv: add Kconfig entries for the F and D ISA
	extensions support
In-Reply-To: <20190521071814.1192-1-tesheng@andestech.com>
References: <20190521071814.1192-1-tesheng@andestech.com>
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To: u-boot@lists.denx.de

Hi Eric,

On Tue, May 21, 2019 at 3:18 PM Eric Lin <tesheng@andestech.com> wrote:
>
> This patch add Kconfig entries for the F (Single-Precision)

adds

> and D (Double-Precision) floating point instruction-set extensions.
>

Could you please provide reason that why U-Boot has to be compiled
using F/D extension?

> Signed-off-by: Eric Lin <tesheng@andestech.com>
> ---
>  arch/riscv/Kconfig  |  8 ++++++++
>  arch/riscv/Makefile | 12 ++++++++----
>  2 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 362f3cdc65..a8031fa230 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -91,6 +91,14 @@ config RISCV_ISA_C
>           when building U-Boot, which results in compressed instructions in the
>           U-Boot binary.
>
> +config RISCV_ISA_F
> +       bool "Emit Floating-point instructions"
> +       default n

this can be dropped as default is n

> +       help
> +         Adds "F" to the ISA subsets that the toolchain is allowed to emit
> +         when building U-Boot, which results in Single and Double-precision instructions

This does not match what the config name says. The config name is for
F and it cannot indicate both F and D here.

> +         in the U-Boot binary.
> +
>  config RISCV_ISA_A
>         def_bool y
>
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index 0b80eb8d86..87ec0ea4b5 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -5,15 +5,19 @@
>
>  ifeq ($(CONFIG_ARCH_RV64I),y)
>         ARCH_BASE = rv64im
> -       ABI = lp64
> +       ABI := lp64
>  endif
>  ifeq ($(CONFIG_ARCH_RV32I),y)
>         ARCH_BASE = rv32im
> -       ABI = ilp32
> +       ABI := ilp32
>  endif
>  ifeq ($(CONFIG_RISCV_ISA_A),y)
>         ARCH_A = a
>  endif
> +ifeq ($(CONFIG_RISCV_ISA_F),y)
> +       ARCH_F = fd
> +       ABI := $(ABI)d
> +endif
>  ifeq ($(CONFIG_RISCV_ISA_C),y)
>         ARCH_C = c
>  endif
> @@ -24,8 +28,8 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
>         CMODEL = medany
>  endif
>
> -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
> -            -mcmodel=$(CMODEL)
> +ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_C) -mabi=$(ABI) \
> +                                -mcmodel=$(CMODEL)
>
>  PLATFORM_CPPFLAGS      += $(ARCH_FLAGS)
>  CFLAGS_EFI             += $(ARCH_FLAGS)
> --

Regards,
Bin