* [PATCH 1/2] x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ
@ 2021-07-28 4:00 Bin Meng
2021-07-28 4:00 ` [PATCH 2/2] x86: dts: Define a default TSC timer frequency Bin Meng
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Bin Meng @ 2021-07-28 4:00 UTC (permalink / raw)
To: u-boot, Simon Glass
Currently there are two places to specify the x86 TSC timer frequency
with one in Kconfig used for early timer and the other one in device
tree used when the frequency cannot be determined from hardware.
This may potentially create an inconsistent config where the 2 values
do not match. Let's use the one specified in Kconfig in the device
tree as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/x86/cpu/quark/Kconfig | 4 ++--
arch/x86/dts/galileo.dts | 2 +-
drivers/timer/Kconfig | 8 ++++----
drivers/timer/tsc_timer.c | 5 +++--
4 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig
index 430cce184d..61bb5792c8 100644
--- a/arch/x86/cpu/quark/Kconfig
+++ b/arch/x86/cpu/quark/Kconfig
@@ -130,8 +130,8 @@ config SYS_CAR_SIZE
Space in bytes in eSRAM used as Cache-As-ARM (CAR).
Note this size must not exceed eSRAM's total size.
-config X86_TSC_TIMER_EARLY_FREQ
+config X86_TSC_TIMER_FREQ
int
- default 400
+ default 400000000
endif
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 501047124e..b5ba1181dd 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -42,7 +42,7 @@
};
tsc-timer {
- clock-frequency = <400000000>;
+ clock-frequency = <CONFIG_X86_TSC_TIMER_FREQ>;
};
mrc {
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index ee81dfa776..8913142654 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -124,12 +124,12 @@ config RENESAS_OSTM_TIMER
Enables support for the Renesas OSTM Timer driver.
This timer is present on Renesas RZ/A1 R7S72100 SoCs.
-config X86_TSC_TIMER_EARLY_FREQ
- int "x86 TSC timer frequency in MHz when used as the early timer"
+config X86_TSC_TIMER_FREQ
+ int "x86 TSC timer frequency in Hz"
depends on X86_TSC_TIMER
- default 1000
+ default 1000000000
help
- Sets the estimated CPU frequency in MHz when TSC is used as the
+ Sets the estimated CPU frequency in Hz when TSC is used as the
early timer and the frequency can neither be calibrated via some
hardware ways, nor got from device tree at the time when device
tree is not available yet.
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 7d19a99622..adef50c374 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -425,12 +425,13 @@ static void tsc_timer_ensure_setup(bool early)
goto done;
if (early)
- fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ;
+ gd->arch.clock_rate = CONFIG_X86_TSC_TIMER_FREQ;
else
return;
done:
- gd->arch.clock_rate = fast_calibrate * 1000000;
+ if (!gd->arch.clock_rate)
+ gd->arch.clock_rate = fast_calibrate * 1000000;
}
gd->arch.tsc_inited = true;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] x86: dts: Define a default TSC timer frequency
2021-07-28 4:00 [PATCH 1/2] x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ Bin Meng
@ 2021-07-28 4:00 ` Bin Meng
2021-07-29 1:32 ` Simon Glass
2021-07-31 1:08 ` [PATCH 1/2] x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ Bin Meng
2021-07-31 1:35 ` Simon Glass
2 siblings, 1 reply; 7+ messages in thread
From: Bin Meng @ 2021-07-28 4:00 UTC (permalink / raw)
To: u-boot, Simon Glass
If for some reason, TSC timer frequency cannot be determined from
hardware, nor is it specified in the device tree, U-Boot will panic
resulting in endless reset during boot.
Let's define a default TSC timer frequency using the Kconfig value
CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of
/include/ otherwise the macro is not pre-processed).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/x86/dts/bayleybay.dts | 2 +-
arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 +-
arch/x86/dts/cherryhill.dts | 2 +-
arch/x86/dts/chromebook_coral.dts | 3 ++-
arch/x86/dts/chromebook_link.dts | 2 +-
arch/x86/dts/chromebook_samus.dts | 2 +-
arch/x86/dts/chromebox_panther.dts | 2 +-
arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +-
arch/x86/dts/coreboot.dts | 7 ++-----
arch/x86/dts/cougarcanyon2.dts | 2 +-
arch/x86/dts/crownbay.dts | 2 +-
arch/x86/dts/edison.dts | 2 +-
arch/x86/dts/efi-x86_app.dts | 7 ++-----
arch/x86/dts/efi-x86_payload.dts | 7 ++-----
arch/x86/dts/galileo.dts | 7 ++-----
arch/x86/dts/minnowmax.dts | 2 +-
arch/x86/dts/qemu-x86_i440fx.dts | 6 +-----
arch/x86/dts/qemu-x86_q35.dts | 6 +-----
arch/x86/dts/slimbootloader.dts | 2 +-
arch/x86/dts/tsc_timer.dtsi | 1 +
20 files changed, 25 insertions(+), 43 deletions(-)
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 70e5798403..828b851773 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
index a7dc03b645..f5d1a28c09 100644
--- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts
index 2ce7f1aa91..99d137e321 100644
--- a/arch/x86/dts/cherryhill.dts
+++ b/arch/x86/dts/cherryhill.dts
@@ -12,8 +12,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index 66c31efb6c..ea879c0300 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -8,7 +8,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
#include "chromeos-x86.dtsi"
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index e529c4b63e..4367fab651 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -9,8 +9,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index ad35ab2e3f..0f0dcdcc5f 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -7,8 +7,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 77b6ac9ab9..0169c427a1 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -4,8 +4,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index bbea99da2c..31eacc2d48 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index 38ddaafa19..d21978d6e0 100644
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -12,7 +12,8 @@
/include/ "pcspkr.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
/ {
model = "coreboot x86 payload";
@@ -30,10 +31,6 @@
stdout-path = "/serial";
};
- tsc-timer {
- clock-frequency = <1000000000>;
- };
-
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
index 602523333e..f850becaaa 100644
--- a/arch/x86/dts/cougarcanyon2.dts
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -12,8 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index a7166a9749..5768352531 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -13,8 +13,8 @@
/include/ "pcspkr.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts
index 8d245bffc2..64b6228363 100644
--- a/arch/x86/dts/edison.dts
+++ b/arch/x86/dts/edison.dts
@@ -10,8 +10,8 @@
/include/ "skeleton.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/efi-x86_app.dts b/arch/x86/dts/efi-x86_app.dts
index 20150f6ede..04e044a07a 100644
--- a/arch/x86/dts/efi-x86_app.dts
+++ b/arch/x86/dts/efi-x86_app.dts
@@ -6,7 +6,8 @@
/dts-v1/;
/include/ "skeleton.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
/ {
model = "EFI x86 Application";
@@ -16,10 +17,6 @@
stdout-path = &serial;
};
- tsc-timer {
- clock-frequency = <1000000000>;
- };
-
serial: serial {
compatible = "efi,uart";
};
diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts
index 5ccb986774..087865f225 100644
--- a/arch/x86/dts/efi-x86_payload.dts
+++ b/arch/x86/dts/efi-x86_payload.dts
@@ -12,7 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
/ {
model = "EFI x86 Payload";
@@ -30,10 +31,6 @@
stdout-path = "/serial";
};
- tsc-timer {
- clock-frequency = <1000000000>;
- };
-
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index b5ba1181dd..4120e8f5c4 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -11,7 +11,8 @@
/include/ "skeleton.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
/ {
model = "Intel Galileo";
@@ -41,10 +42,6 @@
};
};
- tsc-timer {
- clock-frequency = <CONFIG_X86_TSC_TIMER_FREQ>;
- };
-
mrc {
compatible = "intel,quark-mrc";
flags = <MRC_FLAG_SCRAMBLE_EN>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 133d55bc20..110450bb55 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -13,8 +13,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index c33a11d593..6556e9ebcd 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -12,8 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@@ -42,10 +42,6 @@
};
};
- tsc-timer {
- clock-frequency = <1000000000>;
- };
-
pci {
compatible = "pci-x86";
#address-cells = <3>;
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 9faae7fb56..d0830892e8 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -22,8 +22,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@@ -53,10 +53,6 @@
};
};
- tsc-timer {
- clock-frequency = <1000000000>;
- };
-
pci {
compatible = "pci-x86";
#address-cells = <3>;
diff --git a/arch/x86/dts/slimbootloader.dts b/arch/x86/dts/slimbootloader.dts
index d04095c4f8..9b581c8489 100644
--- a/arch/x86/dts/slimbootloader.dts
+++ b/arch/x86/dts/slimbootloader.dts
@@ -7,7 +7,7 @@
/include/ "skeleton.dtsi"
/include/ "reset.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
/ {
model = "slimbootloader x86 payload";
diff --git a/arch/x86/dts/tsc_timer.dtsi b/arch/x86/dts/tsc_timer.dtsi
index 4f5021d96f..4df8e9d7fc 100644
--- a/arch/x86/dts/tsc_timer.dtsi
+++ b/arch/x86/dts/tsc_timer.dtsi
@@ -1,6 +1,7 @@
/ {
tsc-timer {
compatible = "x86,tsc-timer";
+ clock-frequency = <CONFIG_X86_TSC_TIMER_FREQ>;
u-boot,dm-pre-reloc;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] x86: dts: Define a default TSC timer frequency
2021-07-28 4:00 ` [PATCH 2/2] x86: dts: Define a default TSC timer frequency Bin Meng
@ 2021-07-29 1:32 ` Simon Glass
2021-07-31 2:00 ` Bin Meng
0 siblings, 1 reply; 7+ messages in thread
From: Simon Glass @ 2021-07-29 1:32 UTC (permalink / raw)
To: Bin Meng; +Cc: U-Boot Mailing List
On Tue, 27 Jul 2021 at 22:00, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> If for some reason, TSC timer frequency cannot be determined from
> hardware, nor is it specified in the device tree, U-Boot will panic
> resulting in endless reset during boot.
>
> Let's define a default TSC timer frequency using the Kconfig value
> CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of
> /include/ otherwise the macro is not pre-processed).
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/x86/dts/bayleybay.dts | 2 +-
> arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 +-
> arch/x86/dts/cherryhill.dts | 2 +-
> arch/x86/dts/chromebook_coral.dts | 3 ++-
> arch/x86/dts/chromebook_link.dts | 2 +-
> arch/x86/dts/chromebook_samus.dts | 2 +-
> arch/x86/dts/chromebox_panther.dts | 2 +-
> arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +-
> arch/x86/dts/coreboot.dts | 7 ++-----
> arch/x86/dts/cougarcanyon2.dts | 2 +-
> arch/x86/dts/crownbay.dts | 2 +-
> arch/x86/dts/edison.dts | 2 +-
> arch/x86/dts/efi-x86_app.dts | 7 ++-----
> arch/x86/dts/efi-x86_payload.dts | 7 ++-----
> arch/x86/dts/galileo.dts | 7 ++-----
> arch/x86/dts/minnowmax.dts | 2 +-
> arch/x86/dts/qemu-x86_i440fx.dts | 6 +-----
> arch/x86/dts/qemu-x86_q35.dts | 6 +-----
> arch/x86/dts/slimbootloader.dts | 2 +-
> arch/x86/dts/tsc_timer.dtsi | 1 +
> 20 files changed, 25 insertions(+), 43 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ
2021-07-28 4:00 [PATCH 1/2] x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ Bin Meng
2021-07-28 4:00 ` [PATCH 2/2] x86: dts: Define a default TSC timer frequency Bin Meng
@ 2021-07-31 1:08 ` Bin Meng
2021-07-31 1:35 ` Simon Glass
2 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2021-07-31 1:08 UTC (permalink / raw)
To: U-Boot Mailing List, Simon Glass
Hi Simon,
On Wed, Jul 28, 2021 at 12:00 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Currently there are two places to specify the x86 TSC timer frequency
> with one in Kconfig used for early timer and the other one in device
> tree used when the frequency cannot be determined from hardware.
>
> This may potentially create an inconsistent config where the 2 values
> do not match. Let's use the one specified in Kconfig in the device
> tree as well.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/x86/cpu/quark/Kconfig | 4 ++--
> arch/x86/dts/galileo.dts | 2 +-
> drivers/timer/Kconfig | 8 ++++----
> drivers/timer/tsc_timer.c | 5 +++--
> 4 files changed, 10 insertions(+), 9 deletions(-)
>
Looks you reviewed the 2nd patch but not this one.
And there are other 2 patches related to x86 rom build. Could you
please take a look?
Regards,
Bin
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ
2021-07-28 4:00 [PATCH 1/2] x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ Bin Meng
2021-07-28 4:00 ` [PATCH 2/2] x86: dts: Define a default TSC timer frequency Bin Meng
2021-07-31 1:08 ` [PATCH 1/2] x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ Bin Meng
@ 2021-07-31 1:35 ` Simon Glass
2021-07-31 1:59 ` Bin Meng
2 siblings, 1 reply; 7+ messages in thread
From: Simon Glass @ 2021-07-31 1:35 UTC (permalink / raw)
To: Bin Meng; +Cc: U-Boot Mailing List
On Tue, 27 Jul 2021 at 22:00, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Currently there are two places to specify the x86 TSC timer frequency
> with one in Kconfig used for early timer and the other one in device
> tree used when the frequency cannot be determined from hardware.
>
> This may potentially create an inconsistent config where the 2 values
> do not match. Let's use the one specified in Kconfig in the device
> tree as well.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/x86/cpu/quark/Kconfig | 4 ++--
> arch/x86/dts/galileo.dts | 2 +-
> drivers/timer/Kconfig | 8 ++++----
> drivers/timer/tsc_timer.c | 5 +++--
> 4 files changed, 10 insertions(+), 9 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ
2021-07-31 1:35 ` Simon Glass
@ 2021-07-31 1:59 ` Bin Meng
0 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2021-07-31 1:59 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List
On Sat, Jul 31, 2021 at 9:35 AM Simon Glass <sjg@chromium.org> wrote:
>
> On Tue, 27 Jul 2021 at 22:00, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Currently there are two places to specify the x86 TSC timer frequency
> > with one in Kconfig used for early timer and the other one in device
> > tree used when the frequency cannot be determined from hardware.
> >
> > This may potentially create an inconsistent config where the 2 values
> > do not match. Let's use the one specified in Kconfig in the device
> > tree as well.
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> > arch/x86/cpu/quark/Kconfig | 4 ++--
> > arch/x86/dts/galileo.dts | 2 +-
> > drivers/timer/Kconfig | 8 ++++----
> > drivers/timer/tsc_timer.c | 5 +++--
> > 4 files changed, 10 insertions(+), 9 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] x86: dts: Define a default TSC timer frequency
2021-07-29 1:32 ` Simon Glass
@ 2021-07-31 2:00 ` Bin Meng
0 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2021-07-31 2:00 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List
On Thu, Jul 29, 2021 at 9:32 AM Simon Glass <sjg@chromium.org> wrote:
>
> On Tue, 27 Jul 2021 at 22:00, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > If for some reason, TSC timer frequency cannot be determined from
> > hardware, nor is it specified in the device tree, U-Boot will panic
> > resulting in endless reset during boot.
> >
> > Let's define a default TSC timer frequency using the Kconfig value
> > CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of
> > /include/ otherwise the macro is not pre-processed).
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> > arch/x86/dts/bayleybay.dts | 2 +-
> > arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 +-
> > arch/x86/dts/cherryhill.dts | 2 +-
> > arch/x86/dts/chromebook_coral.dts | 3 ++-
> > arch/x86/dts/chromebook_link.dts | 2 +-
> > arch/x86/dts/chromebook_samus.dts | 2 +-
> > arch/x86/dts/chromebox_panther.dts | 2 +-
> > arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +-
> > arch/x86/dts/coreboot.dts | 7 ++-----
> > arch/x86/dts/cougarcanyon2.dts | 2 +-
> > arch/x86/dts/crownbay.dts | 2 +-
> > arch/x86/dts/edison.dts | 2 +-
> > arch/x86/dts/efi-x86_app.dts | 7 ++-----
> > arch/x86/dts/efi-x86_payload.dts | 7 ++-----
> > arch/x86/dts/galileo.dts | 7 ++-----
> > arch/x86/dts/minnowmax.dts | 2 +-
> > arch/x86/dts/qemu-x86_i440fx.dts | 6 +-----
> > arch/x86/dts/qemu-x86_q35.dts | 6 +-----
> > arch/x86/dts/slimbootloader.dts | 2 +-
> > arch/x86/dts/tsc_timer.dtsi | 1 +
> > 20 files changed, 25 insertions(+), 43 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-07-31 2:00 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-28 4:00 [PATCH 1/2] x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ Bin Meng
2021-07-28 4:00 ` [PATCH 2/2] x86: dts: Define a default TSC timer frequency Bin Meng
2021-07-29 1:32 ` Simon Glass
2021-07-31 2:00 ` Bin Meng
2021-07-31 1:08 ` [PATCH 1/2] x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ Bin Meng
2021-07-31 1:35 ` Simon Glass
2021-07-31 1:59 ` Bin Meng
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.