[U-Boot] [PATCH] ata: ahci: enable bus mastering

[U-Boot] [PATCH] ata: ahci: enable bus mastering

[Christian Gmeiner]

When using the coreboot target CONFIG_DM_SCSI gets set to y. This has the effect
that the current 'enable bus mastering' logic gets not compiled in. This change
fixes ahci problems I am seeing on an Intel Apollolake device.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
---
 drivers/ata/ahci.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index e3135bb75f..3f9348a8b3 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1174,6 +1174,12 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
 int ahci_probe_scsi_pci(struct udevice *ahci_dev)
 {
 	ulong base;
+	u16 cmd;
+
+	/* Enable bus mastering. */
+	dm_pci_read_config16(ahci_dev, PCI_COMMAND, &cmd);
+	cmd |= PCI_COMMAND_MASTER;
+	dm_pci_write_config16(ahci_dev, PCI_COMMAND, cmd);
 
 	base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
 				     PCI_REGION_MEM);
-- 
2.21.0

[U-Boot] [PATCH] ata: ahci: enable bus mastering

[Simon Glass]

Hi Christian,

On Wed, 22 May 2019 at 02:40, Christian Gmeiner
<christian.gmeiner@gmail.com> wrote:
>
> When using the coreboot target CONFIG_DM_SCSI gets set to y. This has the effect
> that the current 'enable bus mastering' logic gets not compiled in. This change

Where is it missing? Is it because U-Boot is not scanning the PCI bus?

> fixes ahci problems I am seeing on an Intel Apollolake device.
>
> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> ---
>  drivers/ata/ahci.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
> index e3135bb75f..3f9348a8b3 100644
> --- a/drivers/ata/ahci.c
> +++ b/drivers/ata/ahci.c
> @@ -1174,6 +1174,12 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
>  int ahci_probe_scsi_pci(struct udevice *ahci_dev)
>  {
>         ulong base;
> +       u16 cmd;
> +
> +       /* Enable bus mastering. */

Please don't put . at the end.

> +       dm_pci_read_config16(ahci_dev, PCI_COMMAND, &cmd);
> +       cmd |= PCI_COMMAND_MASTER;
> +       dm_pci_write_config16(ahci_dev, PCI_COMMAND, cmd);

See dm_pci_clrset_config16()

>
>         base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
>                                      PCI_REGION_MEM);
> --
> 2.21.0
>

Regards,
Simon

[U-Boot] [PATCH] ata: ahci: enable bus mastering

[Bin Meng]

Hi Christian,

On Thu, May 23, 2019 at 2:40 AM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Christian,
>
> On Wed, 22 May 2019 at 02:40, Christian Gmeiner
> <christian.gmeiner@gmail.com> wrote:
> >
> > When using the coreboot target CONFIG_DM_SCSI gets set to y. This has the effect
> > that the current 'enable bus mastering' logic gets not compiled in. This change
>
> Where is it missing? Is it because U-Boot is not scanning the PCI bus?

If this is the case, we should fix similar issue on other devices, not
just only SATA.

>
> > fixes ahci problems I am seeing on an Intel Apollolake device.
> >
> > Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> > ---
> >  drivers/ata/ahci.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >

Regards,
Bin

[U-Boot] [PATCH] ata: ahci: enable bus mastering

[Christian Gmeiner]

Hi Simon,

Am Mi., 22. Mai 2019 um 20:40 Uhr schrieb Simon Glass <sjg@chromium.org>:
>
> Hi Christian,
>
> On Wed, 22 May 2019 at 02:40, Christian Gmeiner
> <christian.gmeiner@gmail.com> wrote:
> >
> > When using the coreboot target CONFIG_DM_SCSI gets set to y. This has the effect
> > that the current 'enable bus mastering' logic gets not compiled in. This change
>
> Where is it missing? Is it because U-Boot is not scanning the PCI bus?
>

PCI bus scanning is all fine - but the driver does not enable bus
mastering which results in:

=> scsi scan
scanning bus for devices...
ahci mmio_base=0xc4f4b000
ahci_host_init: start
cap 0xe536ff01 port_map 0x3 n_ports 2
SATA link ok.
Spinning up device on SATA port 0... Target spinup took 0 ms.
ok.
PORT_SCR_ERR 0x0
PORT_IRQ_STAT 0x0
SATA port 0 status: 0x123
SATA link 1 timeout.
HOST_CTL 0x80000000
HOST_CTL 0x80000002
AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
flags: 64bit ncq pm clo only pmp pio slum part apst
Enter start port: 0
Port 0 status: 123
cmd_slot = 7a88e800
cmd_tbl_dma = 7a88ea00
Exit start port 0
Can not start port 0
Enter ahci_device_data_io: for port 0
ahci_dcache_flush_range: flush dcache: [0x7a88e800, 0x7a88f100)
ahci_dcache_flush_range: flush dcache: [0x7a875340, 0x7a875540)
timeout exit!
scsi_ahci: SCSI inquiry command failure.
SCSI command 0x12 ret errno -5
Enter ahci_device_data_io: for port 1
No Link on port 1!
scsi_ahci: SCSI inquiry command failure.
SCSI command 0x12 ret errno -5
=>

> > fixes ahci problems I am seeing on an Intel Apollolake device.
> >
> > Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> > ---
> >  drivers/ata/ahci.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
> > index e3135bb75f..3f9348a8b3 100644
> > --- a/drivers/ata/ahci.c
> > +++ b/drivers/ata/ahci.c
> > @@ -1174,6 +1174,12 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
> >  int ahci_probe_scsi_pci(struct udevice *ahci_dev)
> >  {
> >         ulong base;
> > +       u16 cmd;
> > +
> > +       /* Enable bus mastering. */
>
> Please don't put . at the end.
>

Ok

> > +       dm_pci_read_config16(ahci_dev, PCI_COMMAND, &cmd);
> > +       cmd |= PCI_COMMAND_MASTER;
> > +       dm_pci_write_config16(ahci_dev, PCI_COMMAND, cmd);
>
> See dm_pci_clrset_config16()
>

Ahhh... sounds fine.

-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info

[U-Boot] [PATCH] ata: ahci: enable bus mastering

[Christian Gmeiner]

Hi Bin,

Am Do., 23. Mai 2019 um 04:17 Uhr schrieb Bin Meng <bmeng.cn@gmail.com>:
>
> Hi Christian,
>
> On Thu, May 23, 2019 at 2:40 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Christian,
> >
> > On Wed, 22 May 2019 at 02:40, Christian Gmeiner
> > <christian.gmeiner@gmail.com> wrote:
> > >
> > > When using the coreboot target CONFIG_DM_SCSI gets set to y. This has the effect
> > > that the current 'enable bus mastering' logic gets not compiled in. This change
> >
> > Where is it missing? Is it because U-Boot is not scanning the PCI bus?
>
> If this is the case, we should fix similar issue on other devices, not
> just only SATA.
>

In the ahci driver there is some bus master stuff - but not build with
the coreboot configuration.
See:
https://git.denx.de/?p=u-boot.git;a=blob;f=drivers/ata/ahci.c;h=e3135bb75fddb303cd3e826f02926df0c25e2cfe;hb=HEAD#l325

Other drivers I am using on this platform are fine and do the bus
master enable thing.
- e1000
- xhci

> >
> > > fixes ahci problems I am seeing on an Intel Apollolake device.
> > >
> > > Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> > > ---
> > >  drivers/ata/ahci.c | 6 ++++++
> > >  1 file changed, 6 insertions(+)
> > >
>

-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info