From mboxrd@z Thu Jan  1 00:00:00 1970
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 8 Dec 2019 12:28:31 +0800
Subject: [PATCH v6 078/102] x86: Enable pinctrl in SPL and TPL
In-Reply-To: <CAEUhbmV7Hpa-4WL-RU4-wY=3DK9nV_r05kF6x9FGqCe+j5JDKA@mail.gmail.com>
References: <20191207044315.51770-1-sjg@chromium.org>
 <20191206213936.v6.78.I9a4dc0e4d3efedbfbd94182e276a7f51665d7c1a@changeid>
 <CAEUhbmV7Hpa-4WL-RU4-wY=3DK9nV_r05kF6x9FGqCe+j5JDKA@mail.gmail.com>
Message-ID: <CAEUhbmXLokpmPnTROK2giqM4Yy6r4Jby9UuiTbONCEM95Nt9Vg@mail.gmail.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On Sun, Dec 8, 2019 at 11:58 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Sat, Dec 7, 2019 at 12:52 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > If these phases are used we typically want to enable pinctrl in then, so
> > that pad setup and GPIO access are possible.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v6: None
> > Changes in v5:
> > - Correct build error in chromebook_samus_tpl
> >
> > Changes in v4: None
> > Changes in v3: None
> > Changes in v2: None
> >
> >  arch/Kconfig                           | 2 ++
> >  configs/chromebook_samus_tpl_defconfig | 2 ++
> >  2 files changed, 4 insertions(+)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!