From: Bin Meng <bmeng.cn@gmail.com>
To: Niklas Cassel <niklas.cassel@wdc.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
Date: Fri, 15 Apr 2022 11:44:36 +0800 [thread overview]
Message-ID: <CAEUhbmXfJdLKa7=MFw-Tqf5rnw+BAVqqZ2fmT+jfPxiVgBQPag@mail.gmail.com> (raw)
In-Reply-To: <20220414155510.1364147-1-niklas.cassel@wdc.com>
On Thu, Apr 14, 2022 at 11:55 PM Niklas Cassel via
<qemu-devel@nongnu.org> wrote:
>
> The device tree property "mmu-type" is currently exported as either
> "riscv,sv32" or "riscv,sv48".
>
> However, the riscv cpu device tree binding [1] has a specific value
> "riscv,none" for a HART without a MMU.
>
> Set the device tree property "mmu-type" to "riscv,none" when the CPU mmu
> option is disabled using rv32,mmu=off or rv64,mmu=off.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v5.17
>
> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
> ---
> hw/riscv/virt.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Niklas Cassel <niklas.cassel@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
Date: Fri, 15 Apr 2022 11:44:36 +0800 [thread overview]
Message-ID: <CAEUhbmXfJdLKa7=MFw-Tqf5rnw+BAVqqZ2fmT+jfPxiVgBQPag@mail.gmail.com> (raw)
In-Reply-To: <20220414155510.1364147-1-niklas.cassel@wdc.com>
On Thu, Apr 14, 2022 at 11:55 PM Niklas Cassel via
<qemu-devel@nongnu.org> wrote:
>
> The device tree property "mmu-type" is currently exported as either
> "riscv,sv32" or "riscv,sv48".
>
> However, the riscv cpu device tree binding [1] has a specific value
> "riscv,none" for a HART without a MMU.
>
> Set the device tree property "mmu-type" to "riscv,none" when the CPU mmu
> option is disabled using rv32,mmu=off or rv64,mmu=off.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v5.17
>
> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
> ---
> hw/riscv/virt.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2022-04-15 3:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-14 15:55 [PATCH] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled Niklas Cassel via
2022-04-14 15:55 ` Niklas Cassel
2022-04-15 3:44 ` Bin Meng [this message]
2022-04-15 3:44 ` Bin Meng
2022-04-15 5:27 ` Frank Chang
2022-04-15 5:27 ` Frank Chang
2022-04-19 2:12 ` Alistair Francis
2022-04-19 2:12 ` Alistair Francis
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