[PATCH 1/5] riscv: ae350: dts: Add SPDX license header

[PATCH 1/5] riscv: ae350: dts: Add SPDX license header

[Bin Meng]

The SPDX license header is currently missing. Add one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/riscv/dts/ae350_32.dts | 2 ++
 arch/riscv/dts/ae350_64.dts | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index a0ab5e9be2..ef110c54ae 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
 /dts-v1/;
 
 #include "binman.dtsi"
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index f654f4809a..6abf42e904 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
 /dts-v1/;
 
 #include "binman.dtsi"
-- 
2.25.1

[PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs

[Bin Meng]

There are two spaces before "debug' in bootargs. Drop one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/riscv/dts/ae350_32.dts | 2 +-
 arch/riscv/dts/ae350_64.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index ef110c54ae..b90351e87b 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -16,7 +16,7 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,38400n8  debug loglevel=7";
+		bootargs = "console=ttyS0,38400n8 debug loglevel=7";
 		stdout-path = "uart0:38400n8";
 	};
 
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 6abf42e904..27ac21c716 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -16,7 +16,7 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,38400n8  debug loglevel=7";
+		bootargs = "console=ttyS0,38400n8 debug loglevel=7";
 		stdout-path = "uart0:38400n8";
 	};
 
-- 
2.25.1

[PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes

[Bin Meng]

PLIC nodes don't have child nodes, so #address-cells is not needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/riscv/dts/ae350_32.dts | 2 --
 arch/riscv/dts/ae350_64.dts | 2 --
 2 files changed, 4 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index b90351e87b..0917b83108 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -135,7 +135,6 @@
 
 		plic0: interrupt-controller@e4000000 {
 			compatible = "riscv,plic0";
-			#address-cells = <1>;
 			#interrupt-cells = <1>;
 			interrupt-controller;
 			reg = <0xe4000000 0x2000000>;
@@ -148,7 +147,6 @@
 
 		plic1: interrupt-controller@e6400000 {
 			compatible = "riscv,plic1";
-			#address-cells = <1>;
 			#interrupt-cells = <1>;
 			interrupt-controller;
 			reg = <0xe6400000 0x400000>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 27ac21c716..564e94a1db 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -135,7 +135,6 @@
 
 		plic0: interrupt-controller@e4000000 {
 			compatible = "riscv,plic0";
-			#address-cells = <2>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			reg = <0x0 0xe4000000 0x0 0x2000000>;
@@ -148,7 +147,6 @@
 
 		plic1: interrupt-controller@e6400000 {
 			compatible = "riscv,plic1";
-			#address-cells = <2>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			reg = <0x0 0xe6400000 0x0 0x400000>;
-- 
2.25.1

[PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit

[Bin Meng]

All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/riscv/dts/ae350_32.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 0917b83108..70576846f2 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -135,7 +135,7 @@
 
 		plic0: interrupt-controller@e4000000 {
 			compatible = "riscv,plic0";
-			#interrupt-cells = <1>;
+			#interrupt-cells = <2>;
 			interrupt-controller;
 			reg = <0xe4000000 0x2000000>;
 			riscv,ndev=<71>;
-- 
2.25.1

[PATCH 5/5] riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config

[Bin Meng]

At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The
intention was to use gdb to load device tree before running U-Boot
SPL/proper from RAM. When we switch to OF_SEPARATE we will have to
use our own DT but without "u-boot,dm-spl" in several essential
nodes, SPL does not boot.

Let's add all the required "u-boot,dm-spl" for SPL config.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/riscv/dts/ae350-u-boot.dtsi | 52 ++++++++++++++++++++++++++++++++
 arch/riscv/dts/ae350_32.dts      |  1 +
 arch/riscv/dts/ae350_64.dts      |  1 +
 3 files changed, 54 insertions(+)
 create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi

diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
new file mode 100644
index 0000000000..0d4201cfae
--- /dev/null
+++ b/arch/riscv/dts/ae350-u-boot.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+	cpus {
+		u-boot,dm-spl;
+		CPU0: cpu@0 {
+			u-boot,dm-spl;
+			CPU0_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		CPU1: cpu@1 {
+			u-boot,dm-spl;
+			CPU1_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		CPU2: cpu@2 {
+			u-boot,dm-spl;
+			CPU2_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		CPU3: cpu@3 {
+			u-boot,dm-spl;
+			CPU3_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+	};
+
+	memory@0 {
+		u-boot,dm-spl;
+	};
+
+	soc {
+		u-boot,dm-spl;
+
+		plic1: interrupt-controller@e6400000 {
+			u-boot,dm-spl;
+		};
+
+		plmt0@e6000000 {
+			u-boot,dm-spl;
+		};
+	};
+
+	serial0: serial@f0300000 {
+		u-boot,dm-spl;
+	};
+
+};
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 70576846f2..083f676333 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -3,6 +3,7 @@
 /dts-v1/;
 
 #include "binman.dtsi"
+#include "ae350-u-boot.dtsi"
 
 / {
 	#address-cells = <1>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 564e94a1db..74cff9122d 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -3,6 +3,7 @@
 /dts-v1/;
 
 #include "binman.dtsi"
+#include "ae350-u-boot.dtsi"
 
 / {
 	#address-cells = <2>;
-- 
2.25.1

Re: [PATCH 1/5] riscv: ae350: dts: Add SPDX license header

[Bin Meng]

On Fri, Jun 4, 2021 at 1:51 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> The SPDX license header is currently missing. Add one.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/riscv/dts/ae350_32.dts | 2 ++
>  arch/riscv/dts/ae350_64.dts | 2 ++
>  2 files changed, 4 insertions(+)
>

Ping for this series?

Re: [PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs

[Rick Chen]

> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> Subject: [PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs
>
> There are two spaces before "debug' in bootargs. Drop one.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/riscv/dts/ae350_32.dts | 2 +-
>  arch/riscv/dts/ae350_64.dts | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Rick Chen <rick@andestech.com>

Re: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config

[Rick Chen]

Hi Bin,

> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> Subject: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config
>
> At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The intention was to use gdb to load device tree before running U-Boot SPL/proper from RAM. When we switch to OF_SEPARATE we will have to use our own DT but without "u-boot,dm-spl" in several essential nodes, SPL does not boot.

Can you describe how do you verify and provide the steps about that
SPL boot fail that I can duplicate it. :)

Thanks,
Rick.

>
> Let's add all the required "u-boot,dm-spl" for SPL config.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/riscv/dts/ae350-u-boot.dtsi | 52 ++++++++++++++++++++++++++++++++
>  arch/riscv/dts/ae350_32.dts      |  1 +
>  arch/riscv/dts/ae350_64.dts      |  1 +
>  3 files changed, 54 insertions(+)
>  create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi
>
> diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
> new file mode 100644
> index 0000000000..0d4201cfae
> --- /dev/null
> +++ b/arch/riscv/dts/ae350-u-boot.dtsi
> @@ -0,0 +1,52 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +/ {
> +       cpus {
> +               u-boot,dm-spl;
> +               CPU0: cpu@0 {
> +                       u-boot,dm-spl;
> +                       CPU0_intc: interrupt-controller {
> +                               u-boot,dm-spl;
> +                       };
> +               };
> +               CPU1: cpu@1 {
> +                       u-boot,dm-spl;
> +                       CPU1_intc: interrupt-controller {
> +                               u-boot,dm-spl;
> +                       };
> +               };
> +               CPU2: cpu@2 {
> +                       u-boot,dm-spl;
> +                       CPU2_intc: interrupt-controller {
> +                               u-boot,dm-spl;
> +                       };
> +               };
> +               CPU3: cpu@3 {
> +                       u-boot,dm-spl;
> +                       CPU3_intc: interrupt-controller {
> +                               u-boot,dm-spl;
> +                       };
> +               };
> +       };
> +
> +       memory@0 {
> +               u-boot,dm-spl;
> +       };
> +
> +       soc {
> +               u-boot,dm-spl;
> +
> +               plic1: interrupt-controller@e6400000 {
> +                       u-boot,dm-spl;
> +               };
> +
> +               plmt0@e6000000 {
> +                       u-boot,dm-spl;
> +               };
> +       };
> +
> +       serial0: serial@f0300000 {
> +               u-boot,dm-spl;
> +       };
> +
> +};
> diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 70576846f2..083f676333 100644
> --- a/arch/riscv/dts/ae350_32.dts
> +++ b/arch/riscv/dts/ae350_32.dts
> @@ -3,6 +3,7 @@
>  /dts-v1/;
>
>  #include "binman.dtsi"
> +#include "ae350-u-boot.dtsi"
>
>  / {
>         #address-cells = <1>;
> diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 564e94a1db..74cff9122d 100644
> --- a/arch/riscv/dts/ae350_64.dts
> +++ b/arch/riscv/dts/ae350_64.dts
> @@ -3,6 +3,7 @@
>  /dts-v1/;
>
>  #include "binman.dtsi"
> +#include "ae350-u-boot.dtsi"
>
>  / {
>         #address-cells = <2>;
> --
> 2.25.1
>
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>
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Re: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config

[Bin Meng]

Hi Rick,

On Wed, Jun 9, 2021 at 3:06 PM Rick Chen <rickchen36@gmail.com> wrote:
>
> Hi Bin,
>
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: Friday, June 04, 2021 1:51 PM
> > To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> > Subject: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config
> >
> > At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The intention was to use gdb to load device tree before running U-Boot SPL/proper from RAM. When we switch to OF_SEPARATE we will have to use our own DT but without "u-boot,dm-spl" in several essential nodes, SPL does not boot.
>
> Can you describe how do you verify and provide the steps about that
> SPL boot fail that I can duplicate it. :)

$ make ae350_rv64_spl_defconfig; make -j
$ make menuconfig (change OF_PRIOR_STAGE to OF_EMBED or OF_SEPARATE)

Load u-boot.bin to RAM

Regards,
Bin

Re: [PATCH 1/5] riscv: ae350: dts: Add SPDX license header

[Leo Liang]

On Fri, Jun 04, 2021 at 01:51:09PM +0800, Bin Meng wrote:
> The SPDX license header is currently missing. Add one.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> 
>  arch/riscv/dts/ae350_32.dts | 2 ++
>  arch/riscv/dts/ae350_64.dts | 2 ++
>  2 files changed, 4 insertions(+)
>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config

[Rick Chen]

HI Bin

> Hi Rick,
>
> On Wed, Jun 9, 2021 at 3:06 PM Rick Chen <rickchen36@gmail.com> wrote:
> >
> > Hi Bin,
> >
> > > From: Bin Meng <bmeng.cn@gmail.com>
> > > Sent: Friday, June 04, 2021 1:51 PM
> > > To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> > > Subject: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config
> > >
> > > At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The intention was to use gdb to load device tree before running U-Boot SPL/proper from RAM. When we switch to OF_SEPARATE we will have to use our own DT but without "u-boot,dm-spl" in several essential nodes, SPL does not boot.
> >
> > Can you describe how do you verify and provide the steps about that
> > SPL boot fail that I can duplicate it. :)
>
> $ make ae350_rv64_spl_defconfig; make -j
> $ make menuconfig (change OF_PRIOR_STAGE to OF_EMBED or OF_SEPARATE)
>
> Load u-boot.bin to RAM

It can boot with OF_EMBED.
But it compile fail with choosing OF_EMBED at the first time, fail
messages as below:

binman: [Errno 2] No such file or directory: 'u-boot.dtb'
Makefile:1084: recipe for target 'all' failed
make: *** [all] Error 1

Thanks,
Rick

>
> Regards,
> Bin

Re: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config

[Bin Meng]

Hi Rick,

On Sat, Jun 12, 2021 at 9:30 PM Rick Chen <rickchen36@gmail.com> wrote:
>
> HI Bin
>
> > Hi Rick,
> >
> > On Wed, Jun 9, 2021 at 3:06 PM Rick Chen <rickchen36@gmail.com> wrote:
> > >
> > > Hi Bin,
> > >
> > > > From: Bin Meng <bmeng.cn@gmail.com>
> > > > Sent: Friday, June 04, 2021 1:51 PM
> > > > To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> > > > Subject: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config
> > > >
> > > > At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The intention was to use gdb to load device tree before running U-Boot SPL/proper from RAM. When we switch to OF_SEPARATE we will have to use our own DT but without "u-boot,dm-spl" in several essential nodes, SPL does not boot.
> > >
> > > Can you describe how do you verify and provide the steps about that
> > > SPL boot fail that I can duplicate it. :)
> >
> > $ make ae350_rv64_spl_defconfig; make -j
> > $ make menuconfig (change OF_PRIOR_STAGE to OF_EMBED or OF_SEPARATE)
> >
> > Load u-boot.bin to RAM
>
> It can boot with OF_EMBED.
> But it compile fail with choosing OF_EMBED at the first time, fail
> messages as below:
>
> binman: [Errno 2] No such file or directory: 'u-boot.dtb'
> Makefile:1084: recipe for target 'all' failed
> make: *** [all] Error 1

Yes, this is a known issue of the binman conversion for SPL. OF_EMBED
is a debugging purpose hence I am inclined to leave it as is.

Regards,
Bin

Re: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config

[Rick Chen]

> Hi Rick,
>
> On Sat, Jun 12, 2021 at 9:30 PM Rick Chen <rickchen36@gmail.com> wrote:
> >
> > HI Bin
> >
> > > Hi Rick,
> > >
> > > On Wed, Jun 9, 2021 at 3:06 PM Rick Chen <rickchen36@gmail.com> wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > > From: Bin Meng <bmeng.cn@gmail.com>
> > > > > Sent: Friday, June 04, 2021 1:51 PM
> > > > > To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> > > > > Subject: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config
> > > > >
> > > > > At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The intention was to use gdb to load device tree before running U-Boot SPL/proper from RAM. When we switch to OF_SEPARATE we will have to use our own DT but without "u-boot,dm-spl" in several essential nodes, SPL does not boot.
> > > >
> > > > Can you describe how do you verify and provide the steps about that
> > > > SPL boot fail that I can duplicate it. :)
> > >
> > > $ make ae350_rv64_spl_defconfig; make -j
> > > $ make menuconfig (change OF_PRIOR_STAGE to OF_EMBED or OF_SEPARATE)
> > >
> > > Load u-boot.bin to RAM
> >
> > It can boot with OF_EMBED.
> > But it compile fail with choosing OF_EMBED at the first time, fail
> > messages as below:
> >
> > binman: [Errno 2] No such file or directory: 'u-boot.dtb'
> > Makefile:1084: recipe for target 'all' failed
> > make: *** [all] Error 1
>
> Yes, this is a known issue of the binman conversion for SPL. OF_EMBED
> is a debugging purpose hence I am inclined to leave it as is.

Reviewed-by: Rick Chen <rick@andestech.com>

>
> Regards,
> Bin

Re: [PATCH 1/5] riscv: ae350: dts: Add SPDX license header

[Rick Chen]

> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> Subject: [PATCH 1/5] riscv: ae350: dts: Add SPDX license header
>
> The SPDX license header is currently missing. Add one.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/riscv/dts/ae350_32.dts | 2 ++
>  arch/riscv/dts/ae350_64.dts | 2 ++
>  2 files changed, 4 insertions(+)

Reviewed-by: Rick Chen <rick@andestech.com>

Re: [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes

[Rick Chen]

> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> Subject: [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
>
> PLIC nodes don't have child nodes, so #address-cells is not needed.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/riscv/dts/ae350_32.dts | 2 --
>  arch/riscv/dts/ae350_64.dts | 2 --
>  2 files changed, 4 deletions(-)

Reviewed-by: Rick Chen <rick@andestech.com>

Re: [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit

[Rick Chen]

> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> Subject: [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
>
> All the device nodes that refer to plic0 as their interrupt parent have 2 cells encoded in their interrupts property, but plic0 only provides 1 cell in #interrupt-cells which is incorrect.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/riscv/dts/ae350_32.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Rick Chen <rick@andestech.com>

Re: [PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs

[Leo Liang]

On Fri, Jun 04, 2021 at 01:51:10PM +0800, Bin Meng wrote:
> There are two spaces before "debug' in bootargs. Drop one.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> 
>  arch/riscv/dts/ae350_32.dts | 2 +-
>  arch/riscv/dts/ae350_64.dts | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes

[Leo Liang]

On Fri, Jun 04, 2021 at 01:51:11PM +0800, Bin Meng wrote:
> PLIC nodes don't have child nodes, so #address-cells is not needed.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> 
>  arch/riscv/dts/ae350_32.dts | 2 --
>  arch/riscv/dts/ae350_64.dts | 2 --
>  2 files changed, 4 deletions(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit

[Leo Liang]

On Fri, Jun 04, 2021 at 01:51:12PM +0800, Bin Meng wrote:
> All the device nodes that refer to plic0 as their interrupt parent
> have 2 cells encoded in their interrupts property, but plic0 only
> provides 1 cell in #interrupt-cells which is incorrect.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> 
>  arch/riscv/dts/ae350_32.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>