From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bin Meng Date: Mon, 18 Mar 2019 13:39:03 +0800 Subject: [U-Boot] [PATCH v3 05/11] riscv: save hart ID in register tp instead of s0 In-Reply-To: <20190317182842.18108-6-lukas.auer@aisec.fraunhofer.de> References: <20190317182842.18108-1-lukas.auer@aisec.fraunhofer.de> <20190317182842.18108-6-lukas.auer@aisec.fraunhofer.de> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, Mar 18, 2019 at 2:29 AM Lukas Auer wrote: > > The hart ID passed by the previous boot stage is currently stored in > register s0. If we divert the control flow inside a function, which is > required as part of multi-hart support, the function epilog may not be > called, clobbering register s0. Save the hart ID in the unallocatable > register tp instead to protect the hart ID. > > Signed-off-by: Lukas Auer > --- > > Changes in v3: > - New patch to save the hart ID in register tp instead of s0 > > Changes in v2: None > > arch/riscv/cpu/start.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng