From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, URI_HEX autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A95BDC2D0A3 for ; Tue, 10 Nov 2020 02:10:30 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D07B920679 for ; Tue, 10 Nov 2020 02:10:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="JZweGDxt" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D07B920679 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:60896 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kcJ76-0005rr-LQ for qemu-devel@archiver.kernel.org; Mon, 09 Nov 2020 21:10:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcJ6L-0005DY-6X for qemu-devel@nongnu.org; Mon, 09 Nov 2020 21:09:41 -0500 Received: from mail-oo1-xc43.google.com ([2607:f8b0:4864:20::c43]:33301) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kcJ6G-000592-VF for qemu-devel@nongnu.org; Mon, 09 Nov 2020 21:09:40 -0500 Received: by mail-oo1-xc43.google.com with SMTP id f8so2222805oou.0 for ; Mon, 09 Nov 2020 18:09:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=F0qboTfVfaq/K5RrQV9ipKoGzFoIdqr+xSluElfaDes=; b=JZweGDxtParg+un/dC4DawWywa8evOxdvc0XlQHf1vENy5XDkmAANIn+bWzcxPiyhN ILlUbjHMt4A3TrnZsmv5DUMz2h7oUaj9orZ7NTdl/6RYCnfyDkoLBklLk9DCQbtnRlff YR3dZC7nWky0gBGGh8Hre2L68B4jc7F9bNRqsDaBHmG2RvPZxgbR3XpYfvnNQPJ8Z7Di qWXRZ8g05slYlAz3bhubunDFRSF7fylJ5o1wfTLRA8gu2XJld4eSwvFS7Zupah/cvZK3 zOLB/a6q6fJHduAt5OllYIdCcbKJzSCkBdqIUDbnMdYCWcSXUl+vq922ag4ZBxYBuDwM FZgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=F0qboTfVfaq/K5RrQV9ipKoGzFoIdqr+xSluElfaDes=; b=N7AiqJ7GAwDe1c1fr3+PDmaZKYzVL5MtwIpsrwNu7ySbv067IporlNs105ImuJ4G+Y f9xhp0UUK7BaILP43jOXgs2aIQkCyOA4+DTO5UGvKKMFVOT1KEAaB/Rb6UtTeGhm86pj 3oTJujyuXxpG56JUM1cUytsSfl9YzD3o5G6EPreHAIgl4tQ4dEjrcdI0N/i3JXK2zRq0 mNDMrROFtVS5gCuKwa2de+In74PJrZ4zwzWdX9Qf3ca0+4Rn6SEkfeEnPmKA6tpXHwMs K4m7LFpXXJUpoYPvMQ+BVByXhbyl6X+ZEZ8u/qIFc/ZNYz1xaU/DM16Y/OGwALQvX4cc ElFg== X-Gm-Message-State: AOAM532Eur4Glty65N868SiZeE0XNFyu2Me48NJ8i2/jyhLNM/8ebtSS ynrS7EEzlegmE6WY+baEoiUZP5hXk4gtF2bSLKed9Ke6NUswIA== X-Google-Smtp-Source: ABdhPJyzCf7nX2v3TqZ3XIVz5Hd7DmLPQtSq2AD79juNiSwNAsfG1nvKgvjK78+MK0bN+AAZxf38nGwPY5m0C3WY154= X-Received: by 2002:a4a:8c4f:: with SMTP id v15mr12314880ooj.52.1604974175334; Mon, 09 Nov 2020 18:09:35 -0800 (PST) MIME-Version: 1.0 References: <20200929190448.31116-1-frank.chang@sifive.com> In-Reply-To: From: Frank Chang Date: Tue, 10 Nov 2020 10:09:24 +0800 Message-ID: Subject: Re: [RFC v5 00/68] support vector extension v1.0 To: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" Content-Type: multipart/alternative; boundary="00000000000098501905b3b72b6d" Received-SPF: pass client-ip=2607:f8b0:4864:20::c43; envelope-from=frank.chang@sifive.com; helo=mail-oo1-xc43.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URI_HEX=0.1 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000098501905b3b72b6d Content-Type: text/plain; charset="UTF-8" ping 2nd~ On Tue, Oct 20, 2020 at 3:42 PM Frank Chang wrote: > On Wed, Sep 30, 2020 at 3:04 AM wrote: > >> From: Frank Chang >> >> This patchset implements the vector extension v1.0 for RISC-V on QEMU. >> >> This patchset is sent as RFC because RVV v1.0 is still in draft state. >> v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 >> patchset. >> >> The port is available here: >> https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v5 >> >> You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=v1.0) >> to run with RVV v1.0 instructions. >> >> Note: This patchset depends on two other patchsets listed in Based-on >> section below so it might not able to be built unless those two >> patchsets are applied. >> >> Changelog: >> >> v5 >> * refactor RVV v1.0 check functions. >> (Thanks to Richard Henderson's bitwise tricks.) >> * relax RV_VLEN_MAX to 1024-bits. >> * implement vstart CSR's behaviors. >> * trigger illegal instruction exception if frm is not valid for >> vector floating-point instructions. >> * rebase on riscv-to-apply.next. >> >> v4 >> * remove explicit float flmul variable in DisasContext. >> * replace floating-point calculations with shift operations to >> improve performance. >> * relax RV_VLEN_MAX to 512-bits. >> >> v3 >> * apply nan-box helpers from Richard Henderson. >> * remove fp16 api changes as they are sent independently in another >> pathcset by Chih-Min Chao. >> * remove all tail elements clear functions as tail elements can >> retain unchanged for either VTA set to undisturbed or agnostic. >> * add fp16 nan-box check generator function. >> * add floating-point rounding mode enum. >> * replace flmul arithmetic with shifts to avoid floating-point >> conversions. >> * add Zvqmac extension. >> * replace gdbstub vector register xml files with dynamic generator. >> * bumped to RVV v1.0. >> * RVV v1.0 related changes: >> * add vlre.v and vsr.v vector whole register >> load/store instructions >> * add vrgatherei16 instruction. >> * rearranged bits in vtype to make vlmul bits into a contiguous >> field. >> >> v2 >> * drop v0.7.1 support. >> * replace invisible return check macros with functions. >> * move mark_vs_dirty() to translators. >> * add SSTATUS_VS flag for s-mode. >> * nan-box scalar fp register for floating-point operations. >> * add gdbstub files for vector registers to allow system-mode >> debugging with GDB. >> >> Based-on: <20200909001647.532249-1-richard.henderson@linaro.org/> >> Based-on: <1596102747-20226-1-git-send-email-chihmin.chao@sifive.com/> >> >> Frank Chang (62): >> target/riscv: drop vector 0.7.1 and add 1.0 support >> target/riscv: Use FIELD_EX32() to extract wd field >> target/riscv: rvv-1.0: introduce writable misa.v field >> target/riscv: rvv-1.0: add translation-time vector context status >> target/riscv: rvv-1.0: remove rvv related codes from fcsr registers >> target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr >> registers >> target/riscv: rvv-1.0: remove MLEN calculations >> target/riscv: rvv-1.0: add fractional LMUL >> target/riscv: rvv-1.0: add VMA and VTA >> target/riscv: rvv-1.0: update check functions >> target/riscv: introduce more imm value modes in translator functions >> target/riscv: rvv:1.0: add translation-time nan-box helper function >> target/riscv: rvv-1.0: configure instructions >> target/riscv: rvv-1.0: stride load and store instructions >> target/riscv: rvv-1.0: index load and store instructions >> target/riscv: rvv-1.0: fix address index overflow bug of indexed >> load/store insns >> target/riscv: rvv-1.0: fault-only-first unit stride load >> target/riscv: rvv-1.0: amo operations >> target/riscv: rvv-1.0: load/store whole register instructions >> target/riscv: rvv-1.0: update vext_max_elems() for load/store insns >> target/riscv: rvv-1.0: take fractional LMUL into vector max elements >> calculation >> target/riscv: rvv-1.0: floating-point square-root instruction >> target/riscv: rvv-1.0: floating-point classify instructions >> target/riscv: rvv-1.0: mask population count instruction >> target/riscv: rvv-1.0: find-first-set mask bit instruction >> target/riscv: rvv-1.0: set-X-first mask bit instructions >> target/riscv: rvv-1.0: iota instruction >> target/riscv: rvv-1.0: element index instruction >> target/riscv: rvv-1.0: allow load element with sign-extended >> target/riscv: rvv-1.0: register gather instructions >> target/riscv: rvv-1.0: integer scalar move instructions >> target/riscv: rvv-1.0: floating-point move instruction >> target/riscv: rvv-1.0: floating-point scalar move instructions >> target/riscv: rvv-1.0: whole register move instructions >> target/riscv: rvv-1.0: integer extension instructions >> target/riscv: rvv-1.0: single-width averaging add and subtract >> instructions >> target/riscv: rvv-1.0: single-width bit shift instructions >> target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow >> target/riscv: rvv-1.0: narrowing integer right shift instructions >> target/riscv: rvv-1.0: widening integer multiply-add instructions >> target/riscv: rvv-1.0: single-width saturating add and subtract >> instructions >> target/riscv: rvv-1.0: integer comparison instructions >> target/riscv: rvv-1.0: floating-point compare instructions >> target/riscv: rvv-1.0: mask-register logical instructions >> target/riscv: rvv-1.0: slide instructions >> target/riscv: rvv-1.0: floating-point slide instructions >> target/riscv: rvv-1.0: narrowing fixed-point clip instructions >> target/riscv: rvv-1.0: single-width floating-point reduction >> target/riscv: rvv-1.0: widening floating-point reduction instructions >> target/riscv: rvv-1.0: single-width scaling shift instructions >> target/riscv: rvv-1.0: remove widening saturating scaled multiply-add >> target/riscv: rvv-1.0: remove vmford.vv and vmford.vf >> target/riscv: rvv-1.0: remove integer extract instruction >> target/riscv: rvv-1.0: floating-point min/max instructions >> target/riscv: introduce floating-point rounding mode enum >> target/riscv: rvv-1.0: floating-point/integer type-convert >> instructions >> target/riscv: rvv-1.0: widening floating-point/integer type-convert >> target/riscv: add "set round to odd" rounding mode helper function >> target/riscv: rvv-1.0: narrowing floating-point/integer type-convert >> target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits >> target/riscv: implement vstart CSR >> target/riscv: trigger illegal instruction exception if frm is not >> valid >> >> Greentime Hu (1): >> target/riscv: rvv-1.0: add vlenb register >> >> Hsiangkai Wang (2): >> target/riscv: gdb: modify gdb csr xml file to align with csr register >> map >> target/riscv: gdb: support vector registers for rv64 & rv32 >> >> LIU Zhiwei (3): >> target/riscv: rvv-1.0: add mstatus VS field >> target/riscv: rvv-1.0: add sstatus VS field >> target/riscv: rvv-1.0: add vcsr register >> >> gdb-xml/riscv-32bit-csr.xml | 18 +- >> gdb-xml/riscv-64bit-csr.xml | 18 +- >> target/riscv/cpu.c | 11 +- >> target/riscv/cpu.h | 95 +- >> target/riscv/cpu_bits.h | 10 + >> target/riscv/cpu_helper.c | 16 +- >> target/riscv/csr.c | 79 +- >> target/riscv/fpu_helper.c | 17 +- >> target/riscv/gdbstub.c | 172 +- >> target/riscv/helper.h | 495 ++-- >> target/riscv/insn32-64.decode | 18 +- >> target/riscv/insn32.decode | 288 +- >> target/riscv/insn_trans/trans_rvv.c.inc | 2430 +++++++++++------ >> target/riscv/internals.h | 22 +- >> target/riscv/translate.c | 72 +- >> target/riscv/vector_helper.c | 3316 +++++++++++------------ >> 16 files changed, 4118 insertions(+), 2959 deletions(-) >> >> -- >> 2.17.1 >> >> > ping~ > --00000000000098501905b3b72b6d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
ping 2nd~

On Tue, Oct 20, 2020 at 3:42 PM Frank Chang <<= a href=3D"mailto:frank.chang@sifive.com">frank.chang@sifive.com> wro= te:
On Wed, Sep 30, 2020 at 3:04 AM <frank.chang@sifive.com> w= rote:
From: Frank Chang <frank.chang@sifive.com>

This patchset implements the vector extension v1.0 for RISC-V on QEMU.

This patchset is sent as RFC because RVV v1.0 is still in draft state.
v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 patchset.=

The port is available here:
https://github.com/sifive/qemu/tree/rvv-1.0-u= pstream-v5

You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=3Dv1.0)<= br> to run with RVV v1.0 instructions.

Note: This patchset depends on two other patchsets listed in Based-on
=C2=A0 =C2=A0 =C2=A0 section below so it might not able to be built unless = those two
=C2=A0 =C2=A0 =C2=A0 patchsets are applied.

Changelog:

v5
=C2=A0 * refactor RVV v1.0 check functions.
=C2=A0 =C2=A0 (Thanks to Richard Henderson's bitwise tricks.)
=C2=A0 * relax RV_VLEN_MAX to 1024-bits.
=C2=A0 * implement vstart CSR's behaviors.
=C2=A0 * trigger illegal instruction exception if frm is not valid for
=C2=A0 =C2=A0 vector floating-point instructions.
=C2=A0 * rebase on riscv-to-apply.next.

v4
=C2=A0 * remove explicit float flmul variable in DisasContext.
=C2=A0 * replace floating-point calculations with shift operations to
=C2=A0 =C2=A0 improve performance.
=C2=A0 * relax RV_VLEN_MAX to 512-bits.

v3
=C2=A0 * apply nan-box helpers from Richard Henderson.
=C2=A0 * remove fp16 api changes as they are sent independently in another<= br> =C2=A0 =C2=A0 pathcset by Chih-Min Chao.
=C2=A0 * remove all tail elements clear functions as tail elements can
=C2=A0 =C2=A0 retain unchanged for either VTA set to undisturbed or agnosti= c.
=C2=A0 * add fp16 nan-box check generator function.
=C2=A0 * add floating-point rounding mode enum.
=C2=A0 * replace flmul arithmetic with shifts to avoid floating-point
=C2=A0 =C2=A0 conversions.
=C2=A0 * add Zvqmac extension.
=C2=A0 * replace gdbstub vector register xml files with dynamic generator.<= br> =C2=A0 * bumped to RVV v1.0.
=C2=A0 * RVV v1.0 related changes:
=C2=A0 =C2=A0 * add vl<nf>re<eew>.v and vs<nf>r.v vector = whole register
=C2=A0 =C2=A0 =C2=A0 load/store instructions
=C2=A0 =C2=A0 * add vrgatherei16 instruction.
=C2=A0 =C2=A0 * rearranged bits in vtype to make vlmul bits into a contiguo= us
=C2=A0 =C2=A0 =C2=A0 field.

v2
=C2=A0 * drop v0.7.1 support.
=C2=A0 * replace invisible return check macros with functions.
=C2=A0 * move mark_vs_dirty() to translators.
=C2=A0 * add SSTATUS_VS flag for s-mode.
=C2=A0 * nan-box scalar fp register for floating-point operations.
=C2=A0 * add gdbstub files for vector registers to allow system-mode
=C2=A0 =C2=A0 debugging with GDB.

Based-on: <20200909001647.532249-1-ri= chard.henderson@linaro.org/>
Based-on: <1596102747-20226-1-gi= t-send-email-chihmin.chao@sifive.com/>

Frank Chang (62):
=C2=A0 target/riscv: drop vector 0.7.1 and add 1.0 support
=C2=A0 target/riscv: Use FIELD_EX32() to extract wd field
=C2=A0 target/riscv: rvv-1.0: introduce writable misa.v field
=C2=A0 target/riscv: rvv-1.0: add translation-time vector context status =C2=A0 target/riscv: rvv-1.0: remove rvv related codes from fcsr registers<= br> =C2=A0 target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr =C2=A0 =C2=A0 registers
=C2=A0 target/riscv: rvv-1.0: remove MLEN calculations
=C2=A0 target/riscv: rvv-1.0: add fractional LMUL
=C2=A0 target/riscv: rvv-1.0: add VMA and VTA
=C2=A0 target/riscv: rvv-1.0: update check functions
=C2=A0 target/riscv: introduce more imm value modes in translator functions=
=C2=A0 target/riscv: rvv:1.0: add translation-time nan-box helper function<= br> =C2=A0 target/riscv: rvv-1.0: configure instructions
=C2=A0 target/riscv: rvv-1.0: stride load and store instructions
=C2=A0 target/riscv: rvv-1.0: index load and store instructions
=C2=A0 target/riscv: rvv-1.0: fix address index overflow bug of indexed
=C2=A0 =C2=A0 load/store insns
=C2=A0 target/riscv: rvv-1.0: fault-only-first unit stride load
=C2=A0 target/riscv: rvv-1.0: amo operations
=C2=A0 target/riscv: rvv-1.0: load/store whole register instructions
=C2=A0 target/riscv: rvv-1.0: update vext_max_elems() for load/store insns<= br> =C2=A0 target/riscv: rvv-1.0: take fractional LMUL into vector max elements=
=C2=A0 =C2=A0 calculation
=C2=A0 target/riscv: rvv-1.0: floating-point square-root instruction
=C2=A0 target/riscv: rvv-1.0: floating-point classify instructions
=C2=A0 target/riscv: rvv-1.0: mask population count instruction
=C2=A0 target/riscv: rvv-1.0: find-first-set mask bit instruction
=C2=A0 target/riscv: rvv-1.0: set-X-first mask bit instructions
=C2=A0 target/riscv: rvv-1.0: iota instruction
=C2=A0 target/riscv: rvv-1.0: element index instruction
=C2=A0 target/riscv: rvv-1.0: allow load element with sign-extended
=C2=A0 target/riscv: rvv-1.0: register gather instructions
=C2=A0 target/riscv: rvv-1.0: integer scalar move instructions
=C2=A0 target/riscv: rvv-1.0: floating-point move instruction
=C2=A0 target/riscv: rvv-1.0: floating-point scalar move instructions
=C2=A0 target/riscv: rvv-1.0: whole register move instructions
=C2=A0 target/riscv: rvv-1.0: integer extension instructions
=C2=A0 target/riscv: rvv-1.0: single-width averaging add and subtract
=C2=A0 =C2=A0 instructions
=C2=A0 target/riscv: rvv-1.0: single-width bit shift instructions
=C2=A0 target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow =C2=A0 target/riscv: rvv-1.0: narrowing integer right shift instructions =C2=A0 target/riscv: rvv-1.0: widening integer multiply-add instructions =C2=A0 target/riscv: rvv-1.0: single-width saturating add and subtract
=C2=A0 =C2=A0 instructions
=C2=A0 target/riscv: rvv-1.0: integer comparison instructions
=C2=A0 target/riscv: rvv-1.0: floating-point compare instructions
=C2=A0 target/riscv: rvv-1.0: mask-register logical instructions
=C2=A0 target/riscv: rvv-1.0: slide instructions
=C2=A0 target/riscv: rvv-1.0: floating-point slide instructions
=C2=A0 target/riscv: rvv-1.0: narrowing fixed-point clip instructions
=C2=A0 target/riscv: rvv-1.0: single-width floating-point reduction
=C2=A0 target/riscv: rvv-1.0: widening floating-point reduction instruction= s
=C2=A0 target/riscv: rvv-1.0: single-width scaling shift instructions
=C2=A0 target/riscv: rvv-1.0: remove widening saturating scaled multiply-ad= d
=C2=A0 target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
=C2=A0 target/riscv: rvv-1.0: remove integer extract instruction
=C2=A0 target/riscv: rvv-1.0: floating-point min/max instructions
=C2=A0 target/riscv: introduce floating-point rounding mode enum
=C2=A0 target/riscv: rvv-1.0: floating-point/integer type-convert
=C2=A0 =C2=A0 instructions
=C2=A0 target/riscv: rvv-1.0: widening floating-point/integer type-convert<= br> =C2=A0 target/riscv: add "set round to odd" rounding mode helper = function
=C2=A0 target/riscv: rvv-1.0: narrowing floating-point/integer type-convert=
=C2=A0 target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
=C2=A0 target/riscv: implement vstart CSR
=C2=A0 target/riscv: trigger illegal instruction exception if frm is not =C2=A0 =C2=A0 valid

Greentime Hu (1):
=C2=A0 target/riscv: rvv-1.0: add vlenb register

Hsiangkai Wang (2):
=C2=A0 target/riscv: gdb: modify gdb csr xml file to align with csr registe= r
=C2=A0 =C2=A0 map
=C2=A0 target/riscv: gdb: support vector registers for rv64 & rv32

LIU Zhiwei (3):
=C2=A0 target/riscv: rvv-1.0: add mstatus VS field
=C2=A0 target/riscv: rvv-1.0: add sstatus VS field
=C2=A0 target/riscv: rvv-1.0: add vcsr register

=C2=A0gdb-xml/riscv-32bit-csr.xml=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0|=C2=A0 =C2=A018 +-
=C2=A0gdb-xml/riscv-64bit-csr.xml=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0|=C2=A0 =C2=A018 +-
=C2=A0target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A011 +-
=C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A095 +-
=C2=A0target/riscv/cpu_bits.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 =C2=A010 +
=C2=A0target/riscv/cpu_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 =C2=A016 +-
=C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A079 +-
=C2=A0target/riscv/fpu_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 =C2=A017 +-
=C2=A0target/riscv/gdbstub.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 172 +-
=C2=A0target/riscv/helper.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0|=C2=A0 495 ++--
=C2=A0target/riscv/insn32-64.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0|=C2=A0 =C2=A018 +-
=C2=A0target/riscv/insn32.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 |=C2=A0 288 +-
=C2=A0target/riscv/insn_trans/trans_rvv.c.inc | 2430 +++++++++++------
=C2=A0target/riscv/internals.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 =C2=A022 +-
=C2=A0target/riscv/translate.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 =C2=A072 +-
=C2=A0target/riscv/vector_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= | 3316 +++++++++++------------
=C2=A016 files changed, 4118 insertions(+), 2959 deletions(-)

--
2.17.1


ping~=C2=A0
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