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Mon, 18 Apr 2022 21:33:37 -0700 (PDT) MIME-Version: 1.0 References: <20220418042222.2464199-1-pulehui@huawei.com> In-Reply-To: <20220418042222.2464199-1-pulehui@huawei.com> From: Andrii Nakryiko Date: Mon, 18 Apr 2022 21:33:26 -0700 Message-ID: Subject: Re: [PATCH bpf-next] libbpf: Support riscv USDT argument parsing logic To: Pu Lehui Cc: bpf , open list , Networking , linux-riscv@lists.infradead.org, Andrii Nakryiko , Alexei Starovoitov , Daniel Borkmann , Martin Lau , Song Liu , Yonghong Song , john fastabend , KP Singh , Paul Walmsley , Palmer Dabbelt , Albert Ou Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Apr 17, 2022 at 8:53 PM Pu Lehui wrote: > > Add riscv-specific USDT argument specification parsing logic. > riscv USDT argument format is shown below: > - Memory dereference case: > "size@off(reg)", e.g. "-8@-88(s0)" > - Constant value case: > "size@val", e.g. "4@5" > - Register read case: > "size@reg", e.g. "-8@a1" > > s8 will be marked as poison while it's a reg of riscv, we need > to alias it in advance. > > Signed-off-by: Pu Lehui > --- Can you please mention briefly the testing you performed as I'm not able to test this locally. > tools/lib/bpf/usdt.c | 107 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 107 insertions(+) > > diff --git a/tools/lib/bpf/usdt.c b/tools/lib/bpf/usdt.c > index 934c25301ac1..b8af409cc763 100644 > --- a/tools/lib/bpf/usdt.c > +++ b/tools/lib/bpf/usdt.c > @@ -10,6 +10,11 @@ > #include > #include > > +/* s8 will be marked as poison while it's a reg of riscv */ > +#if defined(__riscv) > +#define rv_s8 s8 > +#endif > + > #include "bpf.h" > #include "libbpf.h" > #include "libbpf_common.h" > @@ -1400,6 +1405,108 @@ static int parse_usdt_arg(const char *arg_str, int arg_num, struct usdt_arg_spec > return len; > } > > +#elif defined(__riscv) > + > +static int calc_pt_regs_off(const char *reg_name) > +{ > + static struct { > + const char *name; > + size_t pt_regs_off; > + } reg_map[] = { > + { "ra", offsetof(struct user_regs_struct, ra) }, > + { "sp", offsetof(struct user_regs_struct, sp) }, > + { "gp", offsetof(struct user_regs_struct, gp) }, > + { "tp", offsetof(struct user_regs_struct, tp) }, > + { "t0", offsetof(struct user_regs_struct, t0) }, > + { "t1", offsetof(struct user_regs_struct, t1) }, > + { "t2", offsetof(struct user_regs_struct, t2) }, > + { "s0", offsetof(struct user_regs_struct, s0) }, > + { "s1", offsetof(struct user_regs_struct, s1) }, > + { "a0", offsetof(struct user_regs_struct, a0) }, > + { "a1", offsetof(struct user_regs_struct, a1) }, > + { "a2", offsetof(struct user_regs_struct, a2) }, > + { "a3", offsetof(struct user_regs_struct, a3) }, > + { "a4", offsetof(struct user_regs_struct, a4) }, > + { "a5", offsetof(struct user_regs_struct, a5) }, > + { "a6", offsetof(struct user_regs_struct, a6) }, > + { "a7", offsetof(struct user_regs_struct, a7) }, > + { "s2", offsetof(struct user_regs_struct, s2) }, > + { "s3", offsetof(struct user_regs_struct, s3) }, > + { "s4", offsetof(struct user_regs_struct, s4) }, > + { "s5", offsetof(struct user_regs_struct, s5) }, > + { "s6", offsetof(struct user_regs_struct, s6) }, > + { "s7", offsetof(struct user_regs_struct, s7) }, > + { "s8", offsetof(struct user_regs_struct, rv_s8) }, > + { "s9", offsetof(struct user_regs_struct, s9) }, > + { "s10", offsetof(struct user_regs_struct, s10) }, > + { "s11", offsetof(struct user_regs_struct, s11) }, > + { "t3", offsetof(struct user_regs_struct, t3) }, > + { "t4", offsetof(struct user_regs_struct, t4) }, > + { "t5", offsetof(struct user_regs_struct, t5) }, > + { "t6", offsetof(struct user_regs_struct, t6) }, would it make sense to order registers a bit more "logically"? Like s0-s11, t0-t6, etc. Right now it looks very random and it's hard to see if all the registers from some range of registers are defined. > + }; > + int i; > + [...] From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0A77C433EF for ; Tue, 19 Apr 2022 04:33:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 18 Apr 2022 21:33:37 -0700 (PDT) MIME-Version: 1.0 References: <20220418042222.2464199-1-pulehui@huawei.com> In-Reply-To: <20220418042222.2464199-1-pulehui@huawei.com> From: Andrii Nakryiko Date: Mon, 18 Apr 2022 21:33:26 -0700 Message-ID: Subject: Re: [PATCH bpf-next] libbpf: Support riscv USDT argument parsing logic To: Pu Lehui Cc: bpf , open list , Networking , linux-riscv@lists.infradead.org, Andrii Nakryiko , Alexei Starovoitov , Daniel Borkmann , Martin Lau , Song Liu , Yonghong Song , john fastabend , KP Singh , Paul Walmsley , Palmer Dabbelt , Albert Ou X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_213340_293946_73621BB7 X-CRM114-Status: GOOD ( 20.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, Apr 17, 2022 at 8:53 PM Pu Lehui wrote: > > Add riscv-specific USDT argument specification parsing logic. > riscv USDT argument format is shown below: > - Memory dereference case: > "size@off(reg)", e.g. "-8@-88(s0)" > - Constant value case: > "size@val", e.g. "4@5" > - Register read case: > "size@reg", e.g. "-8@a1" > > s8 will be marked as poison while it's a reg of riscv, we need > to alias it in advance. > > Signed-off-by: Pu Lehui > --- Can you please mention briefly the testing you performed as I'm not able to test this locally. > tools/lib/bpf/usdt.c | 107 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 107 insertions(+) > > diff --git a/tools/lib/bpf/usdt.c b/tools/lib/bpf/usdt.c > index 934c25301ac1..b8af409cc763 100644 > --- a/tools/lib/bpf/usdt.c > +++ b/tools/lib/bpf/usdt.c > @@ -10,6 +10,11 @@ > #include > #include > > +/* s8 will be marked as poison while it's a reg of riscv */ > +#if defined(__riscv) > +#define rv_s8 s8 > +#endif > + > #include "bpf.h" > #include "libbpf.h" > #include "libbpf_common.h" > @@ -1400,6 +1405,108 @@ static int parse_usdt_arg(const char *arg_str, int arg_num, struct usdt_arg_spec > return len; > } > > +#elif defined(__riscv) > + > +static int calc_pt_regs_off(const char *reg_name) > +{ > + static struct { > + const char *name; > + size_t pt_regs_off; > + } reg_map[] = { > + { "ra", offsetof(struct user_regs_struct, ra) }, > + { "sp", offsetof(struct user_regs_struct, sp) }, > + { "gp", offsetof(struct user_regs_struct, gp) }, > + { "tp", offsetof(struct user_regs_struct, tp) }, > + { "t0", offsetof(struct user_regs_struct, t0) }, > + { "t1", offsetof(struct user_regs_struct, t1) }, > + { "t2", offsetof(struct user_regs_struct, t2) }, > + { "s0", offsetof(struct user_regs_struct, s0) }, > + { "s1", offsetof(struct user_regs_struct, s1) }, > + { "a0", offsetof(struct user_regs_struct, a0) }, > + { "a1", offsetof(struct user_regs_struct, a1) }, > + { "a2", offsetof(struct user_regs_struct, a2) }, > + { "a3", offsetof(struct user_regs_struct, a3) }, > + { "a4", offsetof(struct user_regs_struct, a4) }, > + { "a5", offsetof(struct user_regs_struct, a5) }, > + { "a6", offsetof(struct user_regs_struct, a6) }, > + { "a7", offsetof(struct user_regs_struct, a7) }, > + { "s2", offsetof(struct user_regs_struct, s2) }, > + { "s3", offsetof(struct user_regs_struct, s3) }, > + { "s4", offsetof(struct user_regs_struct, s4) }, > + { "s5", offsetof(struct user_regs_struct, s5) }, > + { "s6", offsetof(struct user_regs_struct, s6) }, > + { "s7", offsetof(struct user_regs_struct, s7) }, > + { "s8", offsetof(struct user_regs_struct, rv_s8) }, > + { "s9", offsetof(struct user_regs_struct, s9) }, > + { "s10", offsetof(struct user_regs_struct, s10) }, > + { "s11", offsetof(struct user_regs_struct, s11) }, > + { "t3", offsetof(struct user_regs_struct, t3) }, > + { "t4", offsetof(struct user_regs_struct, t4) }, > + { "t5", offsetof(struct user_regs_struct, t5) }, > + { "t6", offsetof(struct user_regs_struct, t6) }, would it make sense to order registers a bit more "logically"? Like s0-s11, t0-t6, etc. Right now it looks very random and it's hard to see if all the registers from some range of registers are defined. > + }; > + int i; > + [...] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv