From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33654) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPPry-0005bp-Cw for qemu-devel@nongnu.org; Mon, 17 Mar 2014 01:13:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPPrt-0002TI-SY for qemu-devel@nongnu.org; Mon, 17 Mar 2014 01:13:50 -0400 Received: from mail-wg0-f45.google.com ([74.125.82.45]:49071) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPPrt-0002Ro-NA for qemu-devel@nongnu.org; Mon, 17 Mar 2014 01:13:45 -0400 Received: by mail-wg0-f45.google.com with SMTP id l18so4074042wgh.28 for ; Sun, 16 Mar 2014 22:13:44 -0700 (PDT) MIME-Version: 1.0 Sender: peter.crosthwaite@petalogix.com In-Reply-To: <1394134385-1727-12-git-send-email-peter.maydell@linaro.org> References: <1394134385-1727-1-git-send-email-peter.maydell@linaro.org> <1394134385-1727-12-git-send-email-peter.maydell@linaro.org> Date: Mon, 17 Mar 2014 15:13:44 +1000 Message-ID: From: Peter Crosthwaite Content-Type: text/plain; charset=ISO-8859-1 Subject: Re: [Qemu-devel] [PATCH v4 11/21] target-arm: Don't mention PMU in debug feature register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Rob Herring , Patch Tracking , Michael Matz , Claudio Fontana , Alexander Graf , "qemu-devel@nongnu.org Developers" , Laurent Desnogues , Dirk Mueller , Will Newton , =?ISO-8859-1?Q?Alex_Benn=E9e?= , "kvmarm@lists.cs.columbia.edu" , Christoffer Dall , Richard Henderson On Fri, Mar 7, 2014 at 5:32 AM, Peter Maydell wrote: > Suppress the ID_AA64DFR0_EL1 PMUVer field, even if the CPU specific > value claims that it exists. QEMU doesn't currently implement it, > and not advertising it prevents the guest from trying to use it > and getting UNDEFs on unimplemented registers. > > Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite > --- > This is arguably a hack, but otherwise Linux tries to prod > half a dozen PMU sysregs. Not really. I think sane self-identification trumps dummy feature advertising. Although there is a consistency argument to be made, as to whether you should also wipe-out any other features advertised by this register and friends (e.g. should TraceVer be set?). Regards, Peter > --- > target-arm/helper.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index c18f1a6..e1672aa 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1929,7 +1929,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) > { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, > .access = PL1_R, .type = ARM_CP_CONST, > - .resetvalue = cpu->id_aa64dfr0 }, > + /* We mask out the PMUVer field, beacuse we don't currently > + * implement the PMU. Not advertising it prevents the guest > + * from trying to use it and getting UNDEFs on registers we > + * don't implement. > + */ > + .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, > { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, > .access = PL1_R, .type = ARM_CP_CONST, > -- > 1.9.0 > >