From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ylk3w-0000lZ-I5 for qemu-devel@nongnu.org; Fri, 24 Apr 2015 16:19:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ylk3r-0007bA-Bj for qemu-devel@nongnu.org; Fri, 24 Apr 2015 16:19:00 -0400 Received: from mail-qk0-f177.google.com ([209.85.220.177]:35475) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ylk3r-0007aw-6y for qemu-devel@nongnu.org; Fri, 24 Apr 2015 16:18:55 -0400 Received: by qkhg7 with SMTP id g7so37183756qkh.2 for ; Fri, 24 Apr 2015 13:18:54 -0700 (PDT) MIME-Version: 1.0 Sender: peter.crosthwaite@petalogix.com In-Reply-To: References: Date: Fri, 24 Apr 2015 13:18:54 -0700 Message-ID: From: Peter Crosthwaite Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH target-arm v5 00/14] Next Generation Xilinx Zynq SoC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "qemu-devel@nongnu.org Developers" Cc: Edgar Iglesias , Peter Maydell , zach.pfeffer@xilinx.com, jues@xilinx.com, Ryota Ozaki , "michals@xilinx.com" On Fri, Apr 24, 2015 at 12:31 PM, Peter Crosthwaite wrote: > Hi Peter and all, > > Xilinx's next gen SoC has been announced. This series adds a SoC and > board. > > Series start with addition of ARM cortex A53 support (P1 and P2). The > Soc skeleton is then added with GIC, EMACs and UARTs are added. The > pre-existing models for GEM and UART are not SoC friendly (no visible > state struct), so those are refactored for SoC. > > Create a model of the EP108 board. Currently this doesn't have any > EP108 specific features but is a usable board exposing the user visible > features of the raw SoC. > > See individual patches for detailed change logs. > > changed since v4: > Addressed PMM and Alistair Reviews > > changed since v3: > Included CPU thread kick fix > Addressed Alistair review > > changed since v2: > Fix CPU child prop adder > Add DTS compat string > > changed since v1: > Addressed Alistair review (individual changes on resp. patches) > Changed board name to EP108 > Changed naming scheme to "zynqmp" / "ZYNQMP" (Michal review) > > Regards, > Peter > > > Peter Crosthwaite (14): > target-arm: cpu64: generalise name of A57 regs > target-arm: cpu64: Add support for cortex-a53 > arm: Introduce Xilinx ZynqMP SoC > arm: xlnx-zynqmp: Add GIC > arm: xlnx-zynqmp: Connect CPU Timers to GIC > net: cadence_gem: Clean up variable names > net: cadence_gem: Split state struct and type into header > arm: xilinx-zynqmp: Add GEM support > char: cadence_uart: Clean up variable names > char: cadence_uart: Split state struct and type into header > arm: xilinx-zynqmp: Add UART support > arm: Add xlnx-ep108 machine > arm: xilinx-ep108: Add external RAM > arm: xilinx-ep108: Add bootloading > > default-configs/aarch64-softmmu.mak | 2 +- > hw/arm/Makefile.objs | 1 + > hw/arm/xlnx-ep108.c | 82 ++++++++++++++++ > hw/arm/xlnx-zynqmp.c | 188 ++++++++++++++++++++++++++++++++++++ > hw/char/cadence_uart.c | 115 +++++++++------------- > hw/net/cadence_gem.c | 95 ++++++------------ > include/hw/arm/xlnx-zynqmp.h | 46 +++++++++ > include/hw/char/cadence_uart.h | 53 ++++++++++ > include/hw/net/cadence_gem.h | 73 ++++++++++++++ > target-arm/cpu64.c | 61 +++++++++++- > 10 files changed, 574 insertions(+), 142 deletions(-) > create mode 100644 hw/arm/xlnx-ep108.c > create mode 100644 hw/arm/xlnx-zynqmp.c > create mode 100644 include/hw/arm/xlnx-zynqmp.h > create mode 100644 include/hw/char/cadence_uart.h > create mode 100644 include/hw/net/cadence_gem.h > > -- > 2.3.6.3.g2cc70ee > > Sorry this has a bug in it. Please ignore. V6 on way. The has_el3 change shouldn't be in. Regards, Peter