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From: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
To: Paul Brook <paul@codesourcery.com>
Cc: peter.maydell@linaro.org, monstr@monstr.eu,
	edgar.iglesias@petalogix.com, qemu-devel@nongnu.org,
	John Linn <john.linn@xilinx.com>,
	duyl@xilinx.com, linnj@xilinx.com, afaerber@suse.de,
	john.williams@petalogix.com
Subject: Re: [Qemu-devel] [RFC PATCH v2 2/4] cadence_ttc: initial version of device model
Date: Wed, 8 Feb 2012 20:35:35 +1000	[thread overview]
Message-ID: <CAEgOgz7naoJVNnSk8EYq-0BmpC9zDzeKq62__mrFWE8VOMacGw@mail.gmail.com> (raw)
In-Reply-To: <201202081015.25639.paul@codesourcery.com>

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2012/2/8 Paul Brook <paul@codesourcery.com>

> > > > Implemented cadence Triple Timer Counter (TCC)
> > >
> > > It looks like you're implementing a periodic timer as sequence of
> chained
> > > oneshot timers.  This is a bad idea.  In qemu interrupt latency may be
> > > high,
> > > so you're likely to suffer from significant time skew.
> > >
> > Ok, I could implemented the wraparound event as a periodic timer and the
> > match events are kicked off as seperate one-shot timers when the wrap
> > around occurs? There would still be a small delay on match events, but it
> > would get rid of the integration effect of lots of little delays (over
> many
> > wrap arounds) add up to a significant skew.
>
> I'm not sure why you need the oneshot timers at all. But then again I'm not
> really sure what the desired semantics are either :-)
>

It would help me if you could describe how these timers operate.
> In particular:
>
> - Are they free running.  i.e. keep counting until explicitly stopped by
> the
> user, or stop when an event occurs.
>

Free running


> - When are interrupts raised.  You mention a user specified match value.
>  Do
> we also get an interrupt on wraparound?
>

Yes, an interrupts occur on wrap around of the 16 bit timer value. There
are three match registers which correspond to three more
 (separately maskable) interrupts which are risen when the timer crosses
that value. My implementation will figure out which of the three events (or
the wraparound) will occur next, and one shot the corresponding period of
time. Note that a match can occur an raise an interrupt without a wrap or
reset occuring. E.G. i could set my timer counting up from 0 and when the
value hits BEEF, i get an interrupt, but the timer still counts all the way
to FFFF before wrapping.


> - What happens when the timer hits the limit (zero if count-down, match
> value
> if count-up)? Does it wrap? or load a fixed value?
>
> Either wrap or load a fixed value, there is a control bit to determine
which.


> If you've got independent wrap and match events then I guess yes, a
> periodic
> wrap plus a oneshot match event is probably appropriate.
>
>
Yes this is the case. I will look into making it happen.


> If wrapping does not generate an interrupt, or wrap and match are
> effectively
> the same thing then you just need to transpose the counter onto a single
> periodic timer.
>


> If the timers can be configured in both periodic and oneshot modes, then
> you
> may want to have different implementations based on that.
>
>
I dont think this will be needed, the match mechanism detail above is more
of an issue and is the underlying reason for the one shot chaining
implementation.


> Paul
>

Peter

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  reply	other threads:[~2012-02-08 10:35 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-02-07  6:19 [Qemu-devel] [RFC PATCH v2 0/4]Zynq-7000 EPP platform model Peter A. G. Crosthwaite
2012-02-07  6:19 ` [Qemu-devel] [RFC PATCH v2 1/4] cadence_uart: initial version of device model Peter A. G. Crosthwaite
2012-02-07  6:19 ` [Qemu-devel] [RFC PATCH v2 2/4] cadence_ttc: " Peter A. G. Crosthwaite
2012-02-07 11:28   ` Paul Brook
2012-02-08  7:27     ` Peter Crosthwaite
2012-02-08 10:15       ` Paul Brook
2012-02-08 10:35         ` Peter Crosthwaite [this message]
2012-02-08 12:35           ` Paul Brook
2012-02-08 12:47             ` Peter Crosthwaite
2012-02-07  6:19 ` [Qemu-devel] [RFC PATCH v2 3/4] cadence_gem: " Peter A. G. Crosthwaite
2012-02-07  6:19 ` [Qemu-devel] [RFC PATCH v2 4/4] xilinx_zynq: machine model initial version Peter A. G. Crosthwaite
2012-02-07 11:25 ` [Qemu-devel] [RFC PATCH v2 0/4]Zynq-7000 EPP platform model Paul Brook
2012-02-08  8:24   ` Peter Crosthwaite

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