From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50352) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WCK2G-0008DS-7V for qemu-devel@nongnu.org; Sat, 08 Feb 2014 21:22:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WCK2B-0007vJ-QZ for qemu-devel@nongnu.org; Sat, 08 Feb 2014 21:22:20 -0500 Received: from mail-wi0-f178.google.com ([209.85.212.178]:61397) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WCK2B-0007v2-I1 for qemu-devel@nongnu.org; Sat, 08 Feb 2014 21:22:15 -0500 Received: by mail-wi0-f178.google.com with SMTP id cc10so1869597wib.11 for ; Sat, 08 Feb 2014 18:22:14 -0800 (PST) MIME-Version: 1.0 Sender: peter.crosthwaite@petalogix.com In-Reply-To: <1391183143-30724-24-git-send-email-peter.maydell@linaro.org> References: <1391183143-30724-1-git-send-email-peter.maydell@linaro.org> <1391183143-30724-24-git-send-email-peter.maydell@linaro.org> Date: Sun, 9 Feb 2014 12:22:14 +1000 Message-ID: From: Peter Crosthwaite Content-Type: text/plain; charset=ISO-8859-1 Subject: Re: [Qemu-devel] [PATCH v2 23/35] target-arm: Implement AArch64 cache invalidate/clean ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Rob Herring , Laurent Desnogues , Patch Tracking , Michael Matz , Alexander Graf , "qemu-devel@nongnu.org Developers" , Claudio Fontana , Dirk Mueller , Will Newton , =?ISO-8859-1?Q?Alex_Benn=E9e?= , "kvmarm@lists.cs.columbia.edu" , Christoffer Dall , Richard Henderson On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote: > Implement all the AArch64 cache invalidate and clean ops > (which are all NOPs since QEMU doesn't emulate the cache). > The only remaining unimplemented cache op is DC ZVA. > > Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite > --- > target-arm/helper.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 82efbfa..b9ed707 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1533,6 +1533,18 @@ static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, > env->pstate |= (value & PSTATE_DAIF); > } > > +static CPAccessResult aa64_cacheop_access(CPUARMState *env, > + const ARMCPRegInfo *ri) > +{ > + /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless > + * SCTLR_EL1.UCI is set. > + */ > + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) { > + return CP_ACCESS_TRAP; > + } > + return CP_ACCESS_OK; > +} > + > static const ARMCPRegInfo v8_cp_reginfo[] = { > /* Minimal set of EL0-visible registers. This will need to be expanded > * significantly for system emulation of AArch64 CPUs. > @@ -1561,6 +1573,41 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, > .access = PL1_R, .type = ARM_CP_CURRENTEL }, > + /* Cache ops: all NOPs since we don't emulate caches */ > + { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, > + .access = PL0_W, .type = ARM_CP_NOP, > + .accessfn = aa64_cacheop_access }, > + { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, > + .access = PL0_W, .type = ARM_CP_NOP, > + .accessfn = aa64_cacheop_access }, > + { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, > + .access = PL0_W, .type = ARM_CP_NOP, > + .accessfn = aa64_cacheop_access }, > + { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, > + .access = PL0_W, .type = ARM_CP_NOP, > + .accessfn = aa64_cacheop_access }, > + { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, > + .access = PL1_W, .type = ARM_CP_NOP }, > REGINFO_SENTINEL > }; > > -- > 1.8.5 > >