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X-Received-From: 2607:f8b0:4864:20::d35 Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: Re: [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Jul 26, 2019 at 2:56 AM Alistair Francis wrote: > From: Atish Patra > > As per the RISC-V spec, Floating Point registers are named as f0..f31 > so lets fix the register names accordingly. > > Signed-off-by: Atish Patra > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f8d07bd20a..af1e9b7690 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -40,10 +40,10 @@ const char * const riscv_int_regnames[] = { > }; > > const char * const riscv_fpr_regnames[] = { > - "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", > - "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", > - "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", > - "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" > + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", > + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", > + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", > + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" > }; > Could you indicate the section of the spec ? By chapter 20 of user spec, the patch changes the floating register name to architecture name but leave the integer register use the ABI name. chihmin > const char * const riscv_excp_names[] = { > -- > 2.22.0 > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.86_2) id 1hs7RI-00029u-1M for mharc-qemu-riscv@gnu.org; Mon, 29 Jul 2019 11:19:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44352) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hs7RF-00023w-Ut for qemu-riscv@nongnu.org; Mon, 29 Jul 2019 11:19:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hs7RE-000350-RG for qemu-riscv@nongnu.org; Mon, 29 Jul 2019 11:19:49 -0400 Received: from mail-io1-xd29.google.com ([2607:f8b0:4864:20::d29]:35979) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hs7RE-00034N-IN for qemu-riscv@nongnu.org; Mon, 29 Jul 2019 11:19:48 -0400 Received: by mail-io1-xd29.google.com with SMTP id o9so17240958iom.3 for ; Mon, 29 Jul 2019 08:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=WAiALMNkzL5uN9MeA97W3K0oNByFyZcmznPBDqq7Mfg=; b=MNUgdHA+VXLTXnxNT+CZ3mZ35wgasz0fMgnC0vyczUFKyLa5LhpUlxtB/Uhfi6zjJt qOjWaaQuEjGcV12AAsiSu7zzVqZpFkI21eFhUo2F3kUnshknd6Rt5qNbPmpabXoDd3TA JOUHO/vVZTLhVN1ainlSyS+PQ5KbxWvSM4/7OgOlkMbKIQH1Wr55N5F86kofYESycsJr OSI3MizvrE5DOo+1+DOHvYXfotFfQQEQwdIMyVXYFtYHOo0KxE8uPQuhwWzkpy2pxrS2 71nQDttFpNOydnfczve0ip9zfzgOuTP4MPkUDwklNwobL393FHo3OKZgOlNkDubYZCcM op6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=WAiALMNkzL5uN9MeA97W3K0oNByFyZcmznPBDqq7Mfg=; b=CSAkMF4y/c3zAn4EpaBDYXzLiIEdQysXSKYxougaXBN6Pu746MMyM7PK43HRR69Pla 5MZZjmJegjWzABhsuMgbvOFmPaoW3u425m5wz74eyzKm/5+OeI41NI8aJOJ4GAOPV9DB cnf/3jfycxWVWaj8chRIbD81fqMC1zNC12nBmkb12rLFrTH8lKydMQmDAATfJWKT4U57 YUec42MiFqlHYiSl5J85h9y2E81r4c5Aaf/nA+I2vRzUBQ0IeFPWwl9WbF83I2nSfKIm gCYHDHMXEPnSXOCWZYyw6gLVr1s+4h5ouYEjvUns8bvbbST1L0HHlxVobmf6vpemnxYA yMiw== X-Gm-Message-State: APjAAAU2MyeZEtjq/pRGaexYAgcyPR74ruM02tiQAZHsVeIULxnIp0pX cFsNvORklYi3OCgl8PmuxjUsKepGb3I1D1Q6Hn+FAw== X-Google-Smtp-Source: APXvYqwDxlwzlziWG2rmZ3MYHWHVSrbJZoc2VKOT+ol4vPkJ036OR/oV9QpSRV2XOPC4wAOhLpEj0H2Urmw2MPMj+58= X-Received: by 2002:a6b:4e1a:: with SMTP id c26mr54148491iob.178.1564413587616; Mon, 29 Jul 2019 08:19:47 -0700 (PDT) MIME-Version: 1.0 References: <4116c27c037b5e7f4822cfd7199724450dc6b5da.1564080680.git.alistair.francis@wdc.com> In-Reply-To: <4116c27c037b5e7f4822cfd7199724450dc6b5da.1564080680.git.alistair.francis@wdc.com> From: Chih-Min Chao Date: Mon, 29 Jul 2019 23:19:36 +0800 Message-ID: To: Alistair Francis Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Alistair Francis , Palmer Dabbelt Content-Type: multipart/alternative; boundary="0000000000002c1d7c058ed36ca1" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d29 Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 29 Jul 2019 15:19:51 -0000 --0000000000002c1d7c058ed36ca1 Content-Type: text/plain; charset="UTF-8" On Fri, Jul 26, 2019 at 2:56 AM Alistair Francis wrote: > From: Atish Patra > > As per the RISC-V spec, Floating Point registers are named as f0..f31 > so lets fix the register names accordingly. > > Signed-off-by: Atish Patra > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f8d07bd20a..af1e9b7690 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -40,10 +40,10 @@ const char * const riscv_int_regnames[] = { > }; > > const char * const riscv_fpr_regnames[] = { > - "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", > - "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", > - "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", > - "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" > + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", > + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", > + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", > + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" > }; > Could you indicate the section of the spec ? By chapter 20 of user spec, the patch changes the floating register name to architecture name but leave the integer register use the ABI name. chihmin > const char * const riscv_excp_names[] = { > -- > 2.22.0 > > > --0000000000002c1d7c058ed36ca1 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Fri, Jul 26, 2019 at 2:56 AM Alistair = Francis <alistair.francis@wd= c.com> wrote:
From: Atish Patra <atish.patra@wdc.com>

As per the RISC-V spec, Floating Point registers are named as f0..f31
so lets fix the register names accordingly.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
=C2=A0target/riscv/cpu.c | 8 ++++----
=C2=A01 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f8d07bd20a..af1e9b7690 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -40,10 +40,10 @@ const char * const riscv_int_regnames[] =3D {
=C2=A0};

=C2=A0const char * const riscv_fpr_regnames[] =3D {
-=C2=A0 "ft0", "ft1", "ft2",=C2=A0 "ft3&= quot;,=C2=A0 "ft4", "ft5", "ft6",=C2=A0 "= ;ft7",
-=C2=A0 "fs0", "fs1", "fa0",=C2=A0 "fa1&= quot;,=C2=A0 "fa2", "fa3", "fa4",=C2=A0 "= ;fa5",
-=C2=A0 "fa6", "fa7", "fs2",=C2=A0 "fs3&= quot;,=C2=A0 "fs4", "fs5", "fs6",=C2=A0 "= ;fs7",
-=C2=A0 "fs8", "fs9", "fs10", "fs11"= ;, "ft8", "ft9", "ft10", "ft11"
+=C2=A0 "f0", "f1", "f2",=C2=A0 "f3"= ;,=C2=A0 "f4", "f5", "f6", "f7", +=C2=A0 "f8", "f9", "f10",=C2=A0 "f11&qu= ot;,=C2=A0 "f12", "f13", "f14", "f15&quo= t;,
+=C2=A0 "f16", "f17", "f18",=C2=A0 "f19&= quot;,=C2=A0 "f20", "f21", "f22", "f23&q= uot;,
+=C2=A0 "f24", "f25", "f26", "f27",= "f28", "f29", "f30", "f31"
=C2=A0};

Could you indicate the section= of the spec ?=C2=A0=C2=A0
By chapter 20 of user spec, the patch = changes the floating register name to architecture name but leave the integ= er register use the ABI name.=C2=A0

chihmin
<= blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-l= eft:1px solid rgb(204,204,204);padding-left:1ex"> =C2=A0const char * const riscv_excp_names[] =3D {
--
2.22.0


--0000000000002c1d7c058ed36ca1--